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1. 发明授权

US5523244A Transistor fabrication method using dielectric protection layers to eliminate emitter defects 失效
标题翻译：使用介质保护层消除发射极缺陷的晶体管制造方法
公开(公告)号：US5523244A
公开(公告)日：1996-06-04
申请号：US359102
申请日：1994-12-19
申请人： Truc Q. Vu , Maw-Rong Chin , Mei F. Li
发明人： Truc Q. Vu , Maw-Rong Chin , Mei F. Li
IPC分类号： H01L21/331 , H01L29/423 , H01L21/265 , H01L49/00
CPC分类号： H01L29/66272 , H01L29/42304 , Y10S148/01 , Y10S148/124
摘要： A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions. The dielectric etch stop (protection) layers (116, 130) are non-critically thick and are fully removed from above an extrinsic base region (142) of the device by wet etching before forming the emitter (152) and base regions (142, 144). The method results in a more uniform, lower resistance base connection, higher chip yields, more uniform device properties, and greater device reliability.
摘要翻译：一种用于制造超自对准双极结型晶体管的方法，其通过在所有可能有害的蚀刻步骤期间提供非临界厚的电介质蚀刻停止（保护）层（116）来减少或消除在临界蚀刻步骤期间引起的发射极缺陷。在潜在有害的蚀刻步骤期间，例如用于形成关键器件结构的干式蚀刻工艺（例如发射极开口124），在半导体表面（110）的发射极区域（152）的上方提供氧化物或其它电介质层（116,130）使用诸如湿式蚀刻的非破坏性蚀刻方法来去除介电保护层（116,130）以形成不太关键的器件结构，和/或形成中间层开口，而不会损坏发射极中的硅表面（152）或其他关键区域。电介质蚀刻停止（保护）层（116,130）在形成发射极（152）和基极区域（142）之前通过湿式蚀刻而非临界厚并且通过湿蚀刻完全从器件的非本征基极区域（142） 144）。该方法导致更均匀，更低电阻基极连接，更高的芯片产量，更均匀的器件性能和更大的器件可靠性。

2. 发明授权

US5807771A Radiation-hard, low power, sub-micron CMOS on a SOI substrate 失效
标题翻译： SOI衬底上的辐射硬，低功率，亚微米CMOS
公开(公告)号：US5807771A
公开(公告)日：1998-09-15
申请号：US658188
申请日：1996-06-04
申请人： Truc Q. Vu , Chen-Chi P. Chang , James S. Cable , Mei F. Li
发明人： Truc Q. Vu , Chen-Chi P. Chang , James S. Cable , Mei F. Li
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , Y10S438/953
摘要： A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both a fabrication and structural complexity favorably comparable to conventional CMOS devices which are not radiation-hard. A method for fabricating the device is disclosed.
摘要翻译：一种在绝缘体上硅（SOI）衬底（12）上以亚微米特征尺寸制造的互补金属氧化物半导体（CMOS）类型的辐射硬的低功率半导体器件。 SOI衬底可以是几种不同的类型。亚微米CMOS SOI器件具有与不辐射硬的传统CMOS器件相当的制造和结构复杂性。公开了一种制造该装置的方法。

3. 发明授权

US5578515A Method for fabricating gate structure for nonvolatile memory device comprising an EEPROM and a latch transistor 失效
标题翻译：一种用于制造包括EEPROM和锁存晶体管的非易失性存储器件的栅极结构的方法
公开(公告)号：US5578515A
公开(公告)日：1996-11-26
申请号：US554220
申请日：1995-11-06
申请人： Chen-Chi P. Chang , Mei F. Li , Truc Q. Vu
发明人： Chen-Chi P. Chang , Mei F. Li , Truc Q. Vu
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L27/11546
摘要： The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions. The fabrication process and thinness of the latch transistor gate improve the linewidth control of other transistors formed on the substrate and the latch transistor by avoiding overetching and reducing the normal etching time for the latch gate, respectively.
摘要翻译：包括EEPROM和锁存晶体管的非易失性存储器件的栅极结构通过在第一多晶硅层中构图EEPROM的浮置栅极而在第二多晶硅层上在浮动栅极上图案化EEPROM的控制栅极，然后集中图案化第二层和第一层以形成锁存晶体管的堆叠栅极。堆叠栅极包括电连接到EEPROM浮置栅极的薄栅极和与薄栅极电隔离的保护层。堆叠栅极设计消除了锁存晶体管沟道与漏极和源极区之间的不必要的多晶硅间隔物，从而改善了存储器件的控制。保护层在锁存晶体管的漏极和源极区域的注入期间防止离子穿透。锁存晶体管栅极的制造工艺和薄度分别通过避免过蚀刻和减小锁存栅的正常蚀刻时间来改善形成在衬底和锁存晶体管上的其它晶体管的线宽控制。

4. 发明授权

US5652448A Nonvolatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US5652448A
公开(公告)日：1997-07-29
申请号：US691475
申请日：1996-08-02
申请人： Chen-Chi Peter Chang , Mei F. Li , Truc Q. Vu
发明人： Chen-Chi Peter Chang , Mei F. Li , Truc Q. Vu
IPC分类号： H01L21/8247 , H01L29/76
CPC分类号： H01L27/11526 , H01L27/11546
摘要： The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions. The fabrication process and thinness of the latch transistor gate improve the linewidth control of other transistors formed on the substrate and the latch transistor by avoiding overetching and reducing the normal etching time for the latch gate, respectively.
摘要翻译：包括EEPROM和锁存晶体管的非易失性存储器件的栅极结构通过在第一多晶硅层中构图EEPROM的浮置栅极而在第二多晶硅层上在浮动栅极上图案化EEPROM的控制栅极，然后集中图案化第二层和第一层以形成锁存晶体管的堆叠栅极。堆叠栅极包括电连接到EEPROM浮置栅极的薄栅极和与薄栅极电隔离的保护层。堆叠栅极设计消除了锁存晶体管沟道与漏极和源极区之间的不必要的多晶硅间隔物，从而改善了存储器件的控制。保护层在锁存晶体管的漏极和源极区域的注入期间防止离子穿透。锁存晶体管栅极的制造工艺和薄度分别通过避免过蚀刻和减小锁存栅的正常蚀刻时间来改善形成在衬底和锁存晶体管上的其它晶体管的线宽控制。

5. 发明授权

US07038288B2 Front side illuminated photodiode with backside bump 有权
公开(公告)号：US07038288B2
公开(公告)日：2006-05-02
申请号：US10669081
申请日：2003-09-23
申请人： Jay Jie Lai , Truc Q. Vu , Gary B. Warren
发明人： Jay Jie Lai , Truc Q. Vu , Gary B. Warren
IPC分类号： H01L31/00
CPC分类号： H01L31/105 , H01L27/1446 , H01L27/14636 , H01L31/0203 , H01L2224/48227 , H01L2224/49107 , H01L2924/12032 , H01L2924/30107 , H01L2224/48091 , H01L2924/00014 , H01L2924/00
摘要： This invention relates to a novel optoelectronic chip with one or more optoelectronic devices, such as photodiodes, fabricated on a front side of a semiconductor wafer and contacts on a backside of the semiconductor wafer. The backside contacts can be contact bumps, which allow the optoelectronic chip to achieve the benefits of flip chip packaging without flipping the optoelectronic chip upside down with respect to a chip carrier. In an optical communication system, a photodiode chip can be backside bumped to a chip carrier or an electronic chip, allowing front side illumination of the photodiode chip. Front side illumination offers many benefits, including improved fiber alignment, reduced manufacturing time, and overall cost reduction.

6. 发明授权

US07479401B2 Front side illuminated photodiode with backside bump 有权
标题翻译：前侧照明光电二极管，带背面凸块
公开(公告)号：US07479401B2
公开(公告)日：2009-01-20
申请号：US11414128
申请日：2006-04-28
申请人： Jay Jie Lai , Truc Q. Vu , Gary B. Warren
发明人： Jay Jie Lai , Truc Q. Vu , Gary B. Warren
IPC分类号： H01L21/00
CPC分类号： H01L31/105 , H01L27/1446 , H01L27/14636 , H01L31/0203 , H01L2224/48227 , H01L2224/49107 , H01L2924/12032 , H01L2924/30107 , H01L2224/48091 , H01L2924/00014 , H01L2924/00
摘要： This invention relates to a novel optoelectronic chip with one or more optoelectronic devices, such as photodiodes, fabricated on a front side of a semiconductor wafer and contacts on a backside of the semiconductor wafer. The backside contacts can be contact bumps, which allow the optoelectronic chip to achieve the benefits of flip chip packaging without flipping the optoelectronic chip upside down with respect to a chip carrier. In an optical communication system, a photodiode chip can be backside bumped to a chip carrier or an electronic chip, allowing front side illumination of the photodiode chip. Front side illumination offers many benefits, including improved fiber alignment, reduced manufacturing time, and overall cost reduction.
摘要翻译：本发明涉及一种具有一个或多个光电子器件（例如光电二极管）的新型光电子芯片，其制造在半导体晶片的正面并接触半导体晶片的背面。背面触点可以是接触凸块，其允许光电芯片实现倒装芯片封装的优点，而不会相对于芯片载体颠倒光电芯片。在光通信系统中，光电二极管芯片可以背面凸起到芯片载体或电子芯片，从而允许光电二极管芯片的前侧照明。前侧照明提供许多优点，包括改进光纤对准，缩短制造时间和降低总体成本。

7. 发明授权

US6140832A Method of utilizing IDDQ tests to screen out defective parts 失效
标题翻译：利用IDDQ测试筛选出有缺陷的部件的方法
公开(公告)号：US6140832A
公开(公告)日：2000-10-31
申请号：US92387
申请日：1998-06-05
申请人： Truc Q. Vu , Emad S. Zawaideh , Nhan T. Do , Glenn M. Kramer
发明人： Truc Q. Vu , Emad S. Zawaideh , Nhan T. Do , Glenn M. Kramer
IPC分类号： G01R31/30 , G01R31/26 , G01R1/04 , G01R31/02 , G06F11/00
CPC分类号： G01R31/3004 , G01R31/3008
摘要： A method that uses effective widths of NMOS and PMOS devices in a digital circuit and their intrinsic junction and subthreshold leakage currents to produce a specification for IDDQ, the range of IDDQ, and the delta of IDDQ between pre- and post-overvoltage stress tests to screen out defective integrated circuits having excessive extrinsic current leakage. The present invention provides for a computer-implemented method that generates an indication of whether IDDQ values associated with integrated circuits that have been tested are within the IDDQ specification or not. This processing eliminates the need for time-intensive and costly burn-in testing on the integrated circuits.
摘要翻译：一种在数字电路中使用NMOS和PMOS器件的有效宽度的方法及其本征结和亚阈值漏电流，以产生IDDQ规格，IDDQ范围和过压前后过压应力测试之间的IDDQ增量筛选出具有过大的外部电流泄漏的有缺陷的集成电路。本发明提供了一种计算机实现的方法，其生成与被测试的集成电路相关联的IDDQ值是否在IDDQ规范内的指示。该处理消除了对集成电路进行耗时和昂贵的老化测试的需要。

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