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1. 发明授权

US5652448A Nonvolatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US5652448A
公开(公告)日：1997-07-29
申请号：US691475
申请日：1996-08-02
申请人： Chen-Chi Peter Chang , Mei F. Li , Truc Q. Vu
发明人： Chen-Chi Peter Chang , Mei F. Li , Truc Q. Vu
IPC分类号： H01L21/8247 , H01L29/76
CPC分类号： H01L27/11526 , H01L27/11546
摘要： The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions. The fabrication process and thinness of the latch transistor gate improve the linewidth control of other transistors formed on the substrate and the latch transistor by avoiding overetching and reducing the normal etching time for the latch gate, respectively.
摘要翻译：包括EEPROM和锁存晶体管的非易失性存储器件的栅极结构通过在第一多晶硅层中构图EEPROM的浮置栅极而在第二多晶硅层上在浮动栅极上图案化EEPROM的控制栅极，然后集中图案化第二层和第一层以形成锁存晶体管的堆叠栅极。堆叠栅极包括电连接到EEPROM浮置栅极的薄栅极和与薄栅极电隔离的保护层。堆叠栅极设计消除了锁存晶体管沟道与漏极和源极区之间的不必要的多晶硅间隔物，从而改善了存储器件的控制。保护层在锁存晶体管的漏极和源极区域的注入期间防止离子穿透。锁存晶体管栅极的制造工艺和薄度分别通过避免过蚀刻和减小锁存栅的正常蚀刻时间来改善形成在衬底和锁存晶体管上的其它晶体管的线宽控制。

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