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1. 发明授权

US5807771A Radiation-hard, low power, sub-micron CMOS on a SOI substrate 失效
标题翻译： SOI衬底上的辐射硬，低功率，亚微米CMOS
公开(公告)号：US5807771A
公开(公告)日：1998-09-15
申请号：US658188
申请日：1996-06-04
申请人： Truc Q. Vu , Chen-Chi P. Chang , James S. Cable , Mei F. Li
发明人： Truc Q. Vu , Chen-Chi P. Chang , James S. Cable , Mei F. Li
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , Y10S438/953
摘要： A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both a fabrication and structural complexity favorably comparable to conventional CMOS devices which are not radiation-hard. A method for fabricating the device is disclosed.
摘要翻译：一种在绝缘体上硅（SOI）衬底（12）上以亚微米特征尺寸制造的互补金属氧化物半导体（CMOS）类型的辐射硬的低功率半导体器件。 SOI衬底可以是几种不同的类型。亚微米CMOS SOI器件具有与不辐射硬的传统CMOS器件相当的制造和结构复杂性。公开了一种制造该装置的方法。

2. 发明授权

US5578515A Method for fabricating gate structure for nonvolatile memory device comprising an EEPROM and a latch transistor 失效
标题翻译：一种用于制造包括EEPROM和锁存晶体管的非易失性存储器件的栅极结构的方法
公开(公告)号：US5578515A
公开(公告)日：1996-11-26
申请号：US554220
申请日：1995-11-06
申请人： Chen-Chi P. Chang , Mei F. Li , Truc Q. Vu
发明人： Chen-Chi P. Chang , Mei F. Li , Truc Q. Vu
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L27/11546
摘要： The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions. The fabrication process and thinness of the latch transistor gate improve the linewidth control of other transistors formed on the substrate and the latch transistor by avoiding overetching and reducing the normal etching time for the latch gate, respectively.
摘要翻译：包括EEPROM和锁存晶体管的非易失性存储器件的栅极结构通过在第一多晶硅层中构图EEPROM的浮置栅极而在第二多晶硅层上在浮动栅极上图案化EEPROM的控制栅极，然后集中图案化第二层和第一层以形成锁存晶体管的堆叠栅极。堆叠栅极包括电连接到EEPROM浮置栅极的薄栅极和与薄栅极电隔离的保护层。堆叠栅极设计消除了锁存晶体管沟道与漏极和源极区之间的不必要的多晶硅间隔物，从而改善了存储器件的控制。保护层在锁存晶体管的漏极和源极区域的注入期间防止离子穿透。锁存晶体管栅极的制造工艺和薄度分别通过避免过蚀刻和减小锁存栅的正常蚀刻时间来改善形成在衬底和锁存晶体管上的其它晶体管的线宽控制。

3. 发明授权

US5523244A Transistor fabrication method using dielectric protection layers to eliminate emitter defects 失效
标题翻译：使用介质保护层消除发射极缺陷的晶体管制造方法
公开(公告)号：US5523244A
公开(公告)日：1996-06-04
申请号：US359102
申请日：1994-12-19
申请人： Truc Q. Vu , Maw-Rong Chin , Mei F. Li
发明人： Truc Q. Vu , Maw-Rong Chin , Mei F. Li
IPC分类号： H01L21/331 , H01L29/423 , H01L21/265 , H01L49/00
CPC分类号： H01L29/66272 , H01L29/42304 , Y10S148/01 , Y10S148/124
摘要： A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions. The dielectric etch stop (protection) layers (116, 130) are non-critically thick and are fully removed from above an extrinsic base region (142) of the device by wet etching before forming the emitter (152) and base regions (142, 144). The method results in a more uniform, lower resistance base connection, higher chip yields, more uniform device properties, and greater device reliability.
摘要翻译：一种用于制造超自对准双极结型晶体管的方法，其通过在所有可能有害的蚀刻步骤期间提供非临界厚的电介质蚀刻停止（保护）层（116）来减少或消除在临界蚀刻步骤期间引起的发射极缺陷。在潜在有害的蚀刻步骤期间，例如用于形成关键器件结构的干式蚀刻工艺（例如发射极开口124），在半导体表面（110）的发射极区域（152）的上方提供氧化物或其它电介质层（116,130）使用诸如湿式蚀刻的非破坏性蚀刻方法来去除介电保护层（116,130）以形成不太关键的器件结构，和/或形成中间层开口，而不会损坏发射极中的硅表面（152）或其他关键区域。电介质蚀刻停止（保护）层（116,130）在形成发射极（152）和基极区域（142）之前通过湿式蚀刻而非临界厚并且通过湿蚀刻完全从器件的非本征基极区域（142） 144）。该方法导致更均匀，更低电阻基极连接，更高的芯片产量，更均匀的器件性能和更大的器件可靠性。

4. 发明授权

US5652448A Nonvolatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US5652448A
公开(公告)日：1997-07-29
申请号：US691475
申请日：1996-08-02
申请人： Chen-Chi Peter Chang , Mei F. Li , Truc Q. Vu
发明人： Chen-Chi Peter Chang , Mei F. Li , Truc Q. Vu
IPC分类号： H01L21/8247 , H01L29/76
CPC分类号： H01L27/11526 , H01L27/11546
摘要： The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions. The fabrication process and thinness of the latch transistor gate improve the linewidth control of other transistors formed on the substrate and the latch transistor by avoiding overetching and reducing the normal etching time for the latch gate, respectively.
摘要翻译：包括EEPROM和锁存晶体管的非易失性存储器件的栅极结构通过在第一多晶硅层中构图EEPROM的浮置栅极而在第二多晶硅层上在浮动栅极上图案化EEPROM的控制栅极，然后集中图案化第二层和第一层以形成锁存晶体管的堆叠栅极。堆叠栅极包括电连接到EEPROM浮置栅极的薄栅极和与薄栅极电隔离的保护层。堆叠栅极设计消除了锁存晶体管沟道与漏极和源极区之间的不必要的多晶硅间隔物，从而改善了存储器件的控制。保护层在锁存晶体管的漏极和源极区域的注入期间防止离子穿透。锁存晶体管栅极的制造工艺和薄度分别通过避免过蚀刻和减小锁存栅的正常蚀刻时间来改善形成在衬底和锁存晶体管上的其它晶体管的线宽控制。

5. 发明授权

US5511036A Flash EEPROM cell and array with bifurcated floating gates 失效
标题翻译：闪存EEPROM单元和具有分叉浮动栅极的阵列
公开(公告)号：US5511036A
公开(公告)日：1996-04-23
申请号：US357825
申请日：1994-12-19
申请人： Joseph E. Farb , Chen-chi P. Chang , Mei F. Li
发明人： Joseph E. Farb , Chen-chi P. Chang , Mei F. Li
IPC分类号： H01L29/423 , H01L29/788 , H01L29/78
CPC分类号： H01L29/7885 , H01L29/42324
摘要： Each unit cell (10) of a flash EEPROM array (50) includes a source (18), a drain (20) and a channel (22) formed in a substrate (12). A thin tunnel oxide layer (32) is formed over the substrate (12) and P-Well (14). A bifurcated floating gate (34) is formed on the tunnel oxide layer (32) overlying the channel (22) , and includes a program arm (34a) which overlaps the drain (20), an erase arm (34b) which overlaps the source (18) and a base (34c) which extends around an end of the channel (22) and interconnects the program and erase arms (34a,34b). A thick gate oxide layer (36,36a) is formed over the floating gate (34), and a control gate (38) is formed over the gate oxide layer (36,36a). A central section of the control gate (38) which overlies a gap (34d) between the program and erase arms (34a, 34b) provides threshold voltage control for erasure. The erase arm (34b) spans the entire width of the channel (22), enabling erasure with low applied voltages. The bifurcated floating gate design automatically compensates for alignment error during fabrication such that the relative areas of the channel (22) which underlie the program/erase arms (34a, 34b) and gap (34d) are independent of the location of the gap (34d).
摘要翻译：闪存EEPROM阵列（50）的每个单元（10）包括源（18），漏极（20）和形成在衬底（12）中的沟道（22）。在衬底（12）和P阱（14）之上形成薄的隧道氧化物层（32）。在沟道（22）上的隧道氧化物层（32）上形成有分叉浮动栅极（34），并且包括与漏极（20）重叠的编程臂（34a），与源极重叠的擦除臂（34b）（18）和围绕通道（22）的一端延伸并使编程和擦除臂（34a，34b）互连的基座（34c）。在浮置栅极（34）上方形成厚栅极氧化层（36,36a），并且在栅极氧化物层（36,36a）上形成控制栅极（38）。在编程和擦除臂（34a，34b）之间的间隙（34d）上的控制门（38）的中心部分提供用于擦除的阈值电压控制。擦除臂（34b）跨越通道（22）的整个宽度，能够以低的施加电压进行擦除。分支浮动门设计在制造期间自动补偿对准误差，使得在编程/擦除臂（34a，34b）和间隙（34d）之下的通道（22）的相对面积与间隙（34d）的位置无关）。

6. 发明授权

US5378909A Flash EEPROM cell having gap between floating gate and drain for high hot electron injection efficiency for programming 失效
标题翻译：闪存EEPROM单元在浮置栅极和漏极之间具有间隙，用于编程的高热电子注入效率
公开(公告)号：US5378909A
公开(公告)日：1995-01-03
申请号：US136852
申请日：1993-10-18
申请人： Chen-chi P. Chang , Mei F. Li
发明人： Chen-chi P. Chang , Mei F. Li
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/78
CPC分类号： H01L29/7885 , Y10S257/90
摘要： A flash or block erase electrically erasable programmable read-only memory (EEPROM) cell (10) includes a substrate (12) having a channel region (22), and a source (28) and a drain (32) formed in the substrate (12) on opposite sides of the channel region (22). A first oxide layer (19), a floating gate (20), a second oxide layer (24) and a control gate (26) are formed over the channel region (22). The cell (10) is programmed by hot electron injection from the drain (32) into the floating gate (20), and erased by Fowler-Nordheim tunneling from the floating gate (20) to the source (28). A gap (36) is provided between a sidewall (20a) of the floating gate (20) and the drain (32) to increase the electric field in the drain depletion region. An oxide sidewall spacer (38) is formed on the first oxide layer (19) in the gap (36) which traps electrons. The gap (36) and sidewall spacer (38) increase the hot electron injection efficiency, and enable programming to be accomplished at high speed, with low applied voltages and at high temperatures.
摘要翻译：闪存或块擦除电可擦除可编程只读存储器（EEPROM）单元（10）包括具有沟道区（22）的衬底（12）和形成在衬底中的源极（28）和漏极（32） 12）在通道区域（22）的相对侧上。第一氧化物层（19），浮动栅极（20），第二氧化物层（24）和控制栅极（26）形成在沟道区域（22）上。通过从漏极（32）到浮动栅极（20）的热电子注入来对单元（10）进行编程，并由Fowler-Nordheim从浮动栅极（20）到源极（28）的隧道擦除。在浮动栅极（20）的侧壁（20a）和漏极（32）之间设置间隙（36），以增加漏极耗尽区域中的电场。在捕获电子的间隙（36）中的第一氧化物层（19）上形成氧化物侧壁间隔物（38）。间隙（36）和侧壁间隔物（38）增加了热电子注入效率，并且能够以低的施加电压和高温实现高速编程。

7. 发明授权

US5343424A Split-gate flash EEPROM cell and array with low voltage erasure 失效
标题翻译：分闸快闪EEPROM单元和阵列具有低电压擦除
公开(公告)号：US5343424A
公开(公告)日：1994-08-30
申请号：US47134
申请日：1993-04-16
申请人： Chen-Chi P. Chang , Mei F. Li
发明人： Chen-Chi P. Chang , Mei F. Li
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/68 , G11C11/34
CPC分类号： H01L29/7885 , H01L27/115 , H01L29/4232
摘要： Each unit cell (10) of a flash EEPROM array (50) includes a control gate (38) having a section (38b) disposed in series between a program section (34a) of a floating gate (34) and a source (18) to provide threshold voltage control for erasure. The floating gate (34) further has an erase section (34b) which extends from the program section (34a) around an end of a channel (22) to the source (18). A thin tunnel oxide layer (32) is formed between an end portion (34c) of the erase section (34b) and an underlying portion of the source (18) which enables the floating gate (34) to be erased by Fowler-Nordheim tunneling from the end portion (34c) through the oxide layer (32) to the source (18) with low applied voltages.
摘要翻译：闪存EEPROM阵列（50）的每个单元（10）包括控制栅极（38），该控制栅极具有串联布置在浮动栅极（34）的节目部分（34a）和源极（18）之间的部分（38b）以提供用于擦除的阈值电压控制。浮动栅极（34）还具有从编程部分（34a）围绕通道（22）的一端延伸到源极（18）的擦除部分（34b）。在擦除部分（34b）的端部（34c）和源极（18）的下部之间形成薄的隧道氧化物层（32），其能够通过Fowler-Nordheim隧穿将浮动栅极（34）擦除从施加电压较低的端部（34c）通过氧化物层（32）到源极（18）。

8. 发明授权

US5137837A Radiation-hard, high-voltage semiconductive device structure fabricated on SOI substrate 失效
标题翻译：在SOI衬底上制造的辐射硬，高电压半导体器件结构
公开(公告)号：US5137837A
公开(公告)日：1992-08-11
申请号：US569304
申请日：1990-08-20
申请人： Chen-Chi P. Chang , Mei F. Li
发明人： Chen-Chi P. Chang , Mei F. Li
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12
CPC分类号： H01L21/76264 , H01L21/76224 , H01L21/76243 , H01L21/84 , H01L27/1203 , H01L21/76267 , H01L21/76281 , Y10S438/953
摘要： Highly doped N- and P-type wells (16a, 16b) in a first silicon layer (16) on an insulator layer (14) of a SIMOX substrate (10). Complementary MOSFET devices (52,54,58,62) are formed in lightly doped N- and P-type active areas (22a, 22b) in a second silicon layer (22) formed on the first silicon layer (16). Adjacent active areas (22a, 22b) and underlying wells (16a, 16b) are isolated from each other by trenches (36,78) filled with a radiation-hard insulator material. Field oxide layers (42,64) are formed of a radiation-hard insulator material, preferably boron phosphorous silicon dioxide glass, over the surface of the second silicon layer (22) except in contact areas (68) of the devices (52,54,58,62). The devices (52,54,58,62) are formed in the upper portions of the active areas (22a, 22b), and are insensitive to the interfacial states of the SIMOX substrate (10). The buried wells (16a, 16b ) under the active areas (22a, 22b) have low resistance and enable the devices (52,54,58,62) to have high snap-back voltages. The absence of sharp edges also eliminates edge leakage upon high dosage irradiation, thus producing devices that are more radiation-resistant.
摘要翻译：在SIMOX基板（10）的绝缘体层（14）上的第一硅层（16）中的高掺杂的N和P型阱（16a，16b）。互补MOSFET器件（52,54,58,62）形成在形成在第一硅层（16）上的第二硅层（22）中的轻掺杂的N和P型有源区（22a，22b）中。相邻的有源区域（22a，22b）和下面的阱（16a，16b）通过填充有辐射 - 硬质绝缘体材料的沟槽（36,78）彼此隔离。在第二硅层（22）的表面上除了装置（52,54）的接触区域（68）之外，场氧化物层（42,64）由辐射 - 硬的绝缘体材料，优选为二氧化硅磷玻璃制成，，58,62）。器件（52,54,58,62）形成在有源区（22a，22b）的上部，并且对SIMOX衬底（10）的界面状态不敏感。有源区（22a，22b）下面的埋置阱（16a，16b）具有低电阻，并使得器件（52,54,58,62）能够具有高的快速恢复电压。没有锋利的边缘也消除了高剂量照射时的边缘泄漏，从而产生更耐辐射的装置。

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