专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2017145211A1 SEMICONDUCTOR SWITCHING ELEMENT 审中-公开
标题翻译：半导体开关元件
公开(公告)号：WO2017145211A1
公开(公告)日：2017-08-31
申请号：PCT/JP2016/005222
申请日：2016-12-26
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , DENSO CORPORATION
发明人： SAITO, Jun , AOI, Sachiko , URAKAMI, Yasushi
IPC分类号： H01L29/78 , H01L29/739 , H01L29/06
CPC分类号： H01L29/7813 , H01L21/047 , H01L21/26586 , H01L29/0623 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/66734 , H01L29/7397
摘要： A trench gate semiconductor switching element is provided. The semiconductor substrate of ths element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench, and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region. The bottom region includes a first bottom region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench and extending from the bottom surface to a first position; and a second bottom region in contact with the gate insulation layer in a second range adjacent to the first range and extending from the bottom surface to a second position lower than the first position.
摘要翻译：提供沟槽栅极半导体开关元件。该元件的半导体衬底包括在沟槽的底表面处与栅极绝缘层接触的第二导电类型底部区域和从与主体区域的下表面接触的位置延伸的第一导电类型第二半导体区域到与底部区域的下表面接触的位置。所述底部区域包括第一底部区域和第二底部区域，所述第一底部区域在所述底表面的第一范围中与所述栅极绝缘层接触，所述第一底部表面位于所述沟槽的长度方向上的端部处并且从所述底表面延伸到第一位置; 以及第二底部区域，所述第二底部区域在与所述第一范围相邻的第二范围内与所述栅极绝缘层接触，并且从所述底面延伸到低于所述第一位置的第二位置。

2. 发明申请

WO2015145939A1 INSULATED GATE TYPE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：绝缘栅型半导体器件
公开(公告)号：WO2015145939A1
公开(公告)日：2015-10-01
申请号：PCT/JP2015/000522
申请日：2015-02-05
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： SAITO, Jun , HAMADA, Kimimori , SOENO, Akitaka , TAKAYA, Hidefumi , AOI, Sachiko , YAMAMOTO, Toshimasa
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L21/76229 , H01L21/761 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7811 , H01L29/7813
摘要： An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.
摘要翻译：提供能够容易地耗尽外周区域的绝缘栅型半导体器件。绝缘栅型半导体器件包括：形成在半导体衬底的前表面中的第一至第四外周沟槽; 位于外周沟槽中的绝缘层; 第五半导体区域是第二导电类型并且形成在暴露于外周沟槽的底表面的范围内; 以及将暴露于第二外周沟槽的底表面的第五半导体区域连接到暴露于第三外周沟槽的底表面的第五半导体区域的连接区域。第二和第三外周沟槽之间的间隙比第一和第二外周沟槽之间的间隙以及第三和第四外周沟槽之间的间隙宽。

3. 发明申请

WO2015098088A1 VERTICAL SEMICONDUCTOR DEVICE 审中-公开
标题翻译：垂直半导体器件
公开(公告)号：WO2015098088A1
公开(公告)日：2015-07-02
申请号：PCT/JP2014/006389
申请日：2014-12-22
申请人： KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO , TOYOTA JIDOSHA KABUSHIKI KAISHA , DENSO CORPORATION
发明人： AOI, Sachiko , WATANABE, Yukihiko , SUZUKI, Katsumi , SUZUKI, Naohiro
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/7397 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/063 , H01L29/1095 , H01L29/1608 , H01L29/7802 , H01L29/7811 , H01L29/7813
摘要： The problem to be solved by the present invention is to improve the withstand voltage of the peripheral region 6 of the semiconductor device 2. A resurf layer 32 and a guard ring 30 are formed in a peripheral region 6 in a position at the surface of the semiconductor substrate. The guard ring 30 is formed more deeply than the resurf layer 32. When the guard ring 30 is shallow and the impurity concentration of the resurf layer 32 is low, the potential distribution at the deep portion of the resurf layer 32 becomes unstable, and the resurf layer 32 does not sufficiently exhibit the effect of improving the withstand voltage. When the guard ring 30 is deep, the impurity concentration of the guard ring 30 is high, the potential distribution at the deep portion of the resurf layer 32 is regulated by the guard ring and the resurf layer 32 sufficiently exhibits the effect of improving the withstand voltage.
摘要翻译：本发明要解决的问题是提高半导体器件2的周边区域6的耐受电压。在周边区域6中形成有再生层32和保护环30，半导体衬底。保护环30形成得比再生层32更深。当保护环30较浅并且再生层32的杂质浓度低时，再生层32的深部的电位分布变得不稳定，再生层32不能充分发挥提高耐压的效果。当保护环30较深时，保护环30的杂质浓度高，再生层32的深部处的电位分布由保护环调节，再生层32充分发挥提高耐受性的效果电压。

4. 发明申请

WO2018083526A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2018083526A1
公开(公告)日：2018-05-11
申请号：PCT/IB2017/001303
申请日：2017-10-30
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , DENSO CORPORATION
发明人： ONISHI, Toru , AOI, Sachiko , URAKAMI, Yasushi
IPC分类号： H01L29/423
摘要： In an end portion of a trench (6), an opening (22) where the end portion (10) of the trench is exposed is formed in a lead-out electrode (20), a side surface of the trench gate electrode (14) on a top surface side of a semiconductor substrate is spaced from a trench side surface (12), and a range adjacent to a boundary line positioned between a top surface (4) of the semiconductor substrate and the trench side surface is covered with a laminated insulating film configured such that an interlayer insulating film is laminated on a gate insulating film. This makes it possible to prevent dielectric breakdown of an insulating film.
摘要翻译：在沟槽（6）的端部中，沟槽的端部（10）暴露的开口（22）形成在引出电极（20）中，侧面在半导体衬底的顶表面侧上的沟槽栅电极（14）的表面与沟槽侧表面（12）隔开，并且邻近位于半导体衬底的顶表面（4）和沟槽侧表面被层叠绝缘膜覆盖，该层叠绝缘膜被配置为使得层间绝缘膜层叠在栅极绝缘膜上。这使得可以防止绝缘膜的绝缘击穿。

5. 发明申请

WO2016199390A1 INSULATED GATE SWITCHING DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：绝缘闸门开关装置及其制造方法
公开(公告)号：WO2016199390A1
公开(公告)日：2016-12-15
申请号：PCT/JP2016/002704
申请日：2016-06-03
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , DENSO CORPORATION
发明人： TAKAYA, Hidefumi , MIZUNO, Shoji , WATANABE, Yukihiko , AOI, Sachiko
IPC分类号： H01L21/336 , H01L29/78 , H01L29/12 , H01L29/06 , H01L29/423
CPC分类号： H01L29/1608 , H01L21/02529 , H01L21/046 , H01L21/0475 , H01L21/049 , H01L29/0623 , H01L29/1095 , H01L29/36 , H01L29/4236 , H01L29/42368 , H01L29/66068 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.
摘要翻译：提供一种制造绝缘栅极开关装置的方法。该方法包括：在第一SiC半导体层的表面中形成第一沟槽; 将p型杂质注入第一沟槽的底表面; 在所述第一沟槽的内表面上沉积第二SiC半导体层以形成第二沟槽; 以及形成栅极绝缘层，栅电极，第一区域和主体区域，使得栅极绝缘层覆盖第二沟槽的内表面，栅电极位于第二沟槽中，第一区域为n- 类型并与栅极绝缘层接触，主体区域为p型，与注入区域分离，并且与第一区域下的栅极绝缘层接触。

6. 发明申请

WO2017134509A1 SCHOTTKY DIODE 审中-公开
标题翻译：肖特基二极管
公开(公告)号：WO2017134509A1
公开(公告)日：2017-08-10
申请号：PCT/IB2017/000051
申请日：2017-01-31
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , DENSO CORPORATION
发明人： NAGAOKA, Tatsuji , AOI, Sachiko , URAKAMI, Yasushi
IPC分类号： H01L29/36 , H01L29/40 , H01L29/872 , H01L29/24
CPC分类号： H01L29/872 , H01L29/1608 , H01L29/2003 , H01L29/24 , H01L29/36 , H01L29/407
摘要： A diode includes: a semiconductor substrate including a first surface including a first range and a second range surrounding the first range, the first surface of the semiconductor substrate protruding in the first range from the second range such that the first surface having a step along a border between the first range and the second range; a first electrode that is in Schottky contact with the first electrode within the first range; an interlayer insulating film that covers the step, the second range, and an end portion of the first electrode; and a field plate electrode conductively connected to the first electrode. The field plate electrode covers a region of the interlayer insulating film covering the end portion of the first electrode and a region of the interlayer insulating film covering the step, and extends onto a region of the interlayer insulating film covering the second range.
摘要翻译：二极管包括：半导体衬底，其包括第一表面和第二范围，所述第一表面包括第一范围和围绕所述第一范围的第二范围，所述半导体衬底的所述第一表面从所述第二范围突出在所述第一范围内，所述第一表面沿着所述第一范围和所述第二范围之间的边界具有台阶; 在第一范围内与第一电极肖特基接触的第一电极; 覆盖所述台阶，所述第二范围以及所述第一电极的端部的层间绝缘膜; 以及与第一电极导电连接的场板电极。场板电极覆盖覆盖第一电极的端部的层间绝缘膜的区域和覆盖台阶的层间绝缘膜的区域，并延伸到覆盖第二区域的层间绝缘膜的区域上。

7. 发明申请

WO2016031252A1 SEMICONDUCTOR DEVICE WITH TRENCH GATE 审中-公开
标题翻译：带TRENCH门的半导体器件
公开(公告)号：WO2016031252A1
公开(公告)日：2016-03-03
申请号：PCT/JP2015/004321
申请日：2015-08-27
申请人： KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO , TOYOTA JIDOSHA KABUSHIKI KAISHA , DENSO CORPORATION
发明人： KUTSUKI, Katsuhiro , AOI, Sachiko , WATANABE, Yukihiko , SOENO, Akitaka , ONOGI, Atsushi , MIMURA, Tomohiro
IPC分类号： H01L29/78 , H01L29/423
CPC分类号： H01L29/7813 , H01L21/0475 , H01L29/045 , H01L29/0623 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/66734
摘要： A semiconductor device is provided with a semiconductor substrate in which a trench for a trench gate extends from a top surface of the semiconductor substrate in a depth direction of the semiconductor substrate. An inclined flat surface is arranged in at least a portion between the top surface of the semiconductor substrate and a side surface of the trench, and the inclined flat surface is inclined with respect to the top surface and the side surface.
摘要翻译：半导体器件设置有半导体衬底，其中用于沟槽栅极的沟槽在半导体衬底的深度方向上从半导体衬底的顶表面延伸。在半导体衬底的顶表面和沟槽的侧表面之间的至少一部分上设置倾斜的平坦表面，并且倾斜的平坦表面相对于顶表面和侧表面倾斜。

8. 发明申请

WO2013110994A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2013110994A1
公开(公告)日：2013-08-01
申请号：PCT/IB2013/000072
申请日：2013-01-23
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , KIMURA, Keisuke , KAMEYAMA, Satoru , KOYAMA, Masaki , AOI, Sachiko
发明人： KIMURA, Keisuke , KAMEYAMA, Satoru , KOYAMA, Masaki , AOI, Sachiko
IPC分类号： H01L29/739 , H01L29/861 , H01L29/08
CPC分类号： H01L27/0664 , H01L29/0646 , H01L29/0834 , H01L29/407 , H01L29/7395 , H01L29/7397 , H01L29/861
摘要： When a semiconductor substrate of a semiconductor device is viewed from above, an isolation region, an IGBT region, and a diode region are all formed adjacent to each other. A deep region that is connected to a body region and an anode region is formed in the isolation region. A drift region is formed extending across the isolation region, the IGBT region, and the diode region, inside the semiconductor substrate. A collector region that extends across the isolation region, the IGBT region and the diode region, and a cathode region positioned in the diode region, are formed in a region exposed on a lower surface of the semiconductor substrate. A boundary between the collector region and the cathode region is in the diode region, in a cross- section that cuts across a boundary between the isolation region and the diode region, and divides the isolation region and the diode region. The collector region formed in the isolation region has a higher dopant impurity concentration than the collector region in the IGBT region.
摘要翻译：当从上方观察半导体器件的半导体衬底时，隔离区域，IGBT区域和二极管区域都彼此相邻地形成。在隔离区域中形成连接到体区和阳极区的深区。在半导体衬底内部跨越隔离区域，IGBT区域和二极管区域形成漂移区域。在半导体衬底的下表面上暴露的区域中形成有跨越隔离区域，IGBT区域和二极管区域以及位于二极管区域中的阴极区域的集电极区域。在二极管区域中，集电极区域和阴极区域之间的边界处于跨越隔离区域和二极管区域之间的边界的横截面中，并且分隔隔离区域和二极管区域。形成在隔离区域的集电极区域的掺杂浓度比IGBT区域的集电极区域高。

9. 发明申请

WO2017145210A1 SEMICONDUCTOR SWITCHING ELEMENT 审中-公开
标题翻译：半导体开关元件
公开(公告)号：WO2017145210A1
公开(公告)日：2017-08-31
申请号：PCT/JP2016/005221
申请日：2016-12-26
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , DENSO CORPORATION
发明人： SAITO, Jun , AOI, Sachiko , URAKAMI, Yasushi
IPC分类号： H01L29/78 , H01L29/739 , H01L29/06
CPC分类号： H01L29/0623 , H01L21/047 , H01L21/26586 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A trench gate semiconductor switching element is provided. The semiconductor substrate of this element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench; and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region, and in contact with the gate insulation layer on a lower side of the body region. The bottom region includes a low concentration region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench; and a high concentration region in contact with the gate insulation layer in a second range of the bottom surface adjacent to the first range.
摘要翻译：提供沟槽栅极半导体开关元件。该元件的半导体衬底包括在沟槽的底表面处与栅极绝缘层接触的第二导电类型底部区域; 以及第一导电型第二半导体区域，从与所述本体区域的下表面接触的位置延伸到与所述底部区域的下表面接触的位置，并且在所述第一导电型第二半导体区域的下侧与所述栅绝缘层接触身体部位。底部区域包括在位于沟槽的长边方向的端部的底面的第一范围内与栅极绝缘层接触的低浓度区域，以及在与第一范围相邻的底表面的第二范围内与栅极绝缘层接触的高浓度区域。

10. 发明申请

WO2017134508A1 SCHOTTKY DIODE 审中-公开
标题翻译：肖特基二极管
公开(公告)号：WO2017134508A1
公开(公告)日：2017-08-10
申请号：PCT/IB2017/000049
申请日：2017-01-31
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , DENSO CORPORATION
发明人： NAGAOKA, Tatsuji , AOI, Sachiko , URAKAMI, Yasushi
IPC分类号： H01L29/872 , H01L29/36 , H01L29/40 , H01L29/06 , H01L29/24
CPC分类号： H01L29/872 , H01L29/0611 , H01L29/0649 , H01L29/1608 , H01L29/2003 , H01L29/24 , H01L29/36 , H01L29/402
摘要： A diode includes a semiconductor substrate; a top surface electrode in contact with a part of the top surface of the semiconductor substrate; and a bottom surface electrode in contact with at least a part of the bottom surface of the semiconductor substrate. The semiconductor substrate includes: an n-type high-concentration layer in ohmic contact with the bottom surface electrode; an n-type intermediate-concentration layer on a part of the n-type high-concentration layer; and an n-type low-concentration layer on a part of the n-type high-concentration layer. The n-type low-concentration layer surrounds the n-type intermediate-concentration layer. The top surface electrode is in Schottky contact with a top surface of the n-type intermediate-concentration layer, and a contact region where the top surface electrode and the semiconductor substrate are in contact extends onto then-type low-concentration layer beyond the n-type intermediate-concentration layer.
摘要翻译：二极管包括半导体衬底; 与半导体衬底的顶表面的一部分接触的顶表面电极; 以及与半导体衬底的底表面的至少一部分接触的底表面电极。该半导体衬底包括：与底面电极欧姆接触的n型高浓度层; 在n型高浓度层的一部分上的n型中浓度层; 以及在n型高浓度层的一部分上的n型低浓度层。 n型低浓度层包围n型中浓度层。上表面电极与n型中浓度层的上表面肖特基接触，并且上表面电极和半导体基板接触的接触区域延伸到超过n型的低浓度层上型中浓度层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式