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1. 发明授权

US6060731A Insulated-gate semiconductor device having a contact region in electrical contact with a body region and a source region 失效
标题翻译：绝缘栅半导体器件具有与主体区域和源极区域电接触的接触区域
公开(公告)号：US6060731A
公开(公告)日：2000-05-09
申请号：US122800
申请日：1998-07-27
申请人： Toshio Murata , Sachiko Kawaji , Takashi Suzuki , Tsutomu Uesugi
发明人： Toshio Murata , Sachiko Kawaji , Takashi Suzuki , Tsutomu Uesugi
IPC分类号： H01L29/06 , H01L29/10 , H01L29/78 , H01L29/788
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/1095 , H01L29/7801 , H01L29/7802 , H01L29/7809 , H01L29/7813
摘要： A MOSFET wherein the formation of a channel in a channel formation region is controlled by a voltage applied to an insulated gate, comprising: a semiconductor substrate; a first semiconductor layer (drain region) of a first conductivity type formed on a surface of the semiconductor substrate; a second semiconductor layer (body region) of a second conductivity type provided within the first semiconductor layer, where a part thereof forms the channel formation region; a third semiconductor layer (source region) of the first conductivity type provided selectively in the second semiconductor layer; and a body contact region in electrical contact with the second semiconductor layer. The body contact region is formed in an area that is separated from an active region by a non-active region. With this structure, parasitic bipolar transistors operate simultaneously throughout the entire device so that a uniform breakdown current is generated, thus preventing element destruction due to current concentrations.
摘要翻译：一种MOSFET，其中沟道形成区中的沟道的形成由施加到绝缘栅的电压控制，包括：半导体衬底; 形成在所述半导体衬底的表面上的第一导电类型的第一半导体层（漏极区）; 设置在第一半导体层内的第二导电类型的第二半导体层（体区），其中一部分形成沟道形成区; 所述第一导电类型的第三半导体层（源极区域）选择性地设置在所述第二半导体层中; 以及与第二半导体层电接触的本体接触区域。身体接触区域形成在通过非活性区域与活性区域分离的区域中。利用这种结构，寄生双极晶体管在整个器件中同时工作，从而产生均匀的击穿电流，从而防止元件由于电流集中而损坏。

2. 发明授权

US06169299A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06169299A
公开(公告)日：2001-01-02
申请号：US09258818
申请日：1999-02-26
申请人： Sachiko Kawaji , Toshio Murata , Masayasu Ishiko , Tsutomu Uesugi
发明人： Sachiko Kawaji , Toshio Murata , Masayasu Ishiko , Tsutomu Uesugi
IPC分类号： H01L2974
CPC分类号： H01L29/749 , H01L29/0649 , H01L29/7455
摘要： The MOS gate thyristor of the present invention has a p+ type anode layer (first semiconductor layer), an n− type base region (second semiconductor layer) with the function of acting as a drift layer, a p− type base region (third semiconductor layer), and an n+ type impurity diffusion layer (fourth semiconductor layer) with the function of acting as a source region. On the surface of the base region, an n+ type floating emitter region (fifth semiconductor layer) is formed, while a first channel region (sixth semiconductor layer) is formed between the impurity diffusion layer and the floating emitter region. At the lower ends of the fourth semiconductor layer and the first channel region an insulation layer is formed. The insulation layer acts to suppress the operation of a parasitic thyristor to ensure a reliable turn-off operation of the transistor. A portion of the semiconductor extends from the n+ type floating emitter region and lies underneath the insulation layer in the direction alongside the principal plane of the p+ type anode layer. The extended semiconductor portion helps broaden the carrier injection path.
摘要翻译：本发明的MOS栅极晶闸管具有p +型阳极层（第一半导体层），具有作为漂移层的功能的n型基极区域（第二半导体层），p型基极区域（第三半导体层层）和具有作为源极区域的功能的n +型杂质扩散层（第四半导体层）。在基极区域的表面上形成n +型浮置发射极区域（第五半导体层），同时在杂质扩散层和浮置发射极区域之间形成第一沟道区域（第六半导体层）。在第四半导体层的下端和第一沟道区域形成绝缘层。绝缘层用于抑制寄生晶闸管的操作，以确保晶体管的可靠的关断操作。半导体的一部分从n +型浮置发射极区域延伸并且位于绝缘层下方沿着p +型阳极层的主平面的方向。延伸的半导体部分有助于拓宽载流子注入路径。

3. 发明授权

US6072215A Semiconductor device including lateral MOS element 失效
标题翻译：包括横向MOS元件的半导体器件
公开(公告)号：US6072215A
公开(公告)日：2000-06-06
申请号：US275868
申请日：1999-03-25
申请人： Sachiko Kawaji , Masahito Kodama , Takashi Suzuki , Tsutomu Uesugi
发明人： Sachiko Kawaji , Masahito Kodama , Takashi Suzuki , Tsutomu Uesugi
IPC分类号： H01L21/331 , H01L21/336 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/786 , H01L29/76 , H01L31/113
CPC分类号： H01L29/66704 , H01L29/0653 , H01L29/41766 , H01L29/42356 , H01L29/4236 , H01L29/66325 , H01L29/66674 , H01L29/7393 , H01L29/7394 , H01L29/7824 , H01L29/7825 , H01L29/7831
摘要： Disclosed is a semiconductor device including a lateral MOS element which comprises a p-type silicon substrate; a first semiconductor layer of an n-type constituting a drift region; a second semiconductor layer of the p-type selectively provided in the first semiconductor layer, and constituting a body region, in which a channel region is partially formed; a third semiconductor layer of the n-type selectively provided in a surface of the second semiconductor layer, and constituting a source region; a fourth semiconductor layer of the n-type provided in the first semiconductor layer, and constituting a drain region; and a trench gate. The trench gate is constructed such that a trench formed in the first semiconductor layer is filled with a gate electrode with an insulating film interposed therebetween. The trench gate is formed such that at least a bottom thereof is in contact with the semiconductor substrate. The semiconductor device of the present invention prevents a high electric field at a corner of the bottom of the trench gate, thus achieving its high breakdown voltage.
摘要翻译：公开了包括p型硅衬底的横向MOS元件的半导体器件; 构成漂移区域的n型的第一半导体层; p型的第二半导体层选择性地设置在第一半导体层中，并且构成其中部分地形成沟道区的体区; n型的第三半导体层选择性地设置在第二半导体层的表面中，并构成源极区; n型的第四半导体层，设置在第一半导体层中，构成漏区; 和一个沟槽门。沟槽栅被构造成使得形成在第一半导体层中的沟槽填充有绝缘膜插入其间的栅电极。沟槽栅极形成为至少其底部与半导体衬底接触。本发明的半导体器件防止沟槽栅极底部拐角处的高电场，从而实现其高击穿电压。

4. 发明授权

US06177704B1 Semiconductor device containing a lateral MOS transistor 有权
标题翻译：半导体器件具有高击穿电压，低导通电阻，侧向功率mosfet
公开(公告)号：US06177704B1
公开(公告)日：2001-01-23
申请号：US09160594
申请日：1998-09-25
申请人： Takashi Suzuki , Sachiko Kawaji , Tsutomu Uesugi
发明人： Takashi Suzuki , Sachiko Kawaji , Tsutomu Uesugi
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L27/1203 , H01L29/0653 , H01L29/41766 , H01L29/7809 , H01L29/7812 , H01L29/7824
摘要： A semiconductor device containing a lateral MOS transistor comprising a silicon substrate, an n-type first semiconductor layer constituting a drain drift region, a p-type second semiconductor layer prepared within the first semiconductor layer to constitute a body region and with a channel region formed within a portion of said body region, an n-type third semiconductor layer prepared on the surface of the second semiconductor layer to constitute a source region, an n-type fourth semiconductor layer constituting a drain region, and an insulation layer that is constituted of insulating material filled into a trench prepared in the first semiconductor layer and arranged along the two sides of the drain region. The drain region is formed into a region deeper than the insulation layer and in contact with the drain drift region at a portion beneath the insulation layer. The semiconductor device provides a high breakdown voltage and a low on-resistance, and can be fabricated with a reduced cell pitch.
摘要翻译：一种半导体器件，包括一个包括硅衬底的横向MOS晶体管，构成漏极漂移区的n型第一半导体层，在第一半导体层内制备的构成体区的p型第二半导体层，以及形成沟道区在所述体区的一部分内，形成在所述第二半导体层的表面上构成源极区域的n型第三半导体层，构成漏极区域的n型第四半导体层，以及由绝缘层构成的绝缘层，绝缘材料填充到在第一半导体层中制备并沿着漏极区域的两侧布置的沟槽中。漏极区域形成为比绝缘层更深的区域，并且在绝缘层下方的部分与漏极漂移区域接触。半导体器件提供高击穿电压和低导通电阻，并且可以以减小的单元间距制造。

5. 发明授权

US06982459B2 Semiconductor device having a vertical type semiconductor element 有权
标题翻译：具有垂直型半导体元件的半导体器件
公开(公告)号：US06982459B2
公开(公告)日：2006-01-03
申请号：US10634819
申请日：2003-08-06
申请人： Takashi Suzuki , Tsutomu Uesugi , Norihito Tokura
发明人： Takashi Suzuki , Tsutomu Uesugi , Norihito Tokura
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/7813
摘要： A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.
摘要翻译：垂直型MOS场效应晶体管在源电极和N + +型漏极区之间具有超结结构。超结结构由多个P型单晶硅区域和多个N型单晶硅区域构成。多个P型单晶硅区域和多个N型单晶硅区域中的每一个交替排列。超结具有两部分，即设置MOS结构的电池形成区域和位于电池形成区域周边的周边区域。源电极接触周边区域中的P型单晶硅区域中的一个，同时远离位于周边区域中最外侧的周边区域的端部设置。

6. 发明授权

US06639260B2 Semiconductor device having a vertical semiconductor element 有权
标题翻译：具有垂直半导体元件的半导体器件
公开(公告)号：US06639260B2
公开(公告)日：2003-10-28
申请号：US10015917
申请日：2001-12-17
申请人： Takashi Suzuki , Tsutomu Uesugi , Norihito Tokura
发明人： Takashi Suzuki , Tsutomu Uesugi , Norihito Tokura
IPC分类号： H01L2976
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/7813
摘要： A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.
摘要翻译：垂直型MOS场效应晶体管在源电极和N +型漏极区之间具有超结结构。超结结构由多个P型单晶硅区域和多个N型单晶硅区域构成。多个P型单晶硅区域和多个N型单晶硅区域中的每一个交替排列。超结具有两部分，即设置MOS结构的电池形成区域和位于电池形成区域周边的周边区域。源电极接触周边区域中的P型单晶硅区域中的一个，同时远离位于周边区域中最外侧的周边区域的端部设置。

7. 发明授权

US07777252B2 III-V hemt devices 有权
标题翻译： III-V血液装置
公开(公告)号：US07777252B2
公开(公告)日：2010-08-17
申请号：US11632665
申请日：2005-06-22
申请人： Masahiro Sugimoto , Tetsu Kachi , Yoshitaka Nakano , Tsutomu Uesugi , Hiroyuki Ueda , Narumasa Soejima
发明人： Masahiro Sugimoto , Tetsu Kachi , Yoshitaka Nakano , Tsutomu Uesugi , Hiroyuki Ueda , Narumasa Soejima
IPC分类号： H01L29/739 , H01L31/072
CPC分类号： H01L29/778 , H01L21/28 , H01L29/2003 , H01L29/66431 , H01L29/66462 , H01L29/7787
摘要： A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm−3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.
摘要翻译：半导体器件具有其中堆叠p-GaN层，SI-GaN层和AlGaN层的堆叠结构，并且具有形成在AlGaN层的顶表面侧的栅电极。 AlGaN层的带隙比p-GaN层和SI-GaN层的带隙宽。此外，SI-GaN层的杂质浓度小于1×1017cm-3。包括III-V半导体的半导体器件可以具有稳定的常关断操作。

8. 发明申请

US20100013006A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100013006A1
公开(公告)日：2010-01-21
申请号：US12502251
申请日：2009-07-14
申请人： Masahiro SUGIMOTO , Tsutomu Uesugi , Masakazu Kanechika , Testsu Kachi
发明人： Masahiro SUGIMOTO , Tsutomu Uesugi , Masakazu Kanechika , Testsu Kachi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/8122 , H01L29/0623 , H01L29/0657 , H01L29/1029 , H01L29/1037 , H01L29/1075 , H01L29/1079 , H01L29/42316 , H01L29/7828 , H01L29/7832 , H01L29/7838 , H01L29/812
摘要： A semiconductor device has a semiconductor substrate having a surface layer and a p-type semiconductor region, wherein the surface layer includes a contact region, a channel region and a drift region, the channel region is adjacent to and in contact with the contact region, the drift region is adjacent to and in contact with the channel region and includes n-type impurities at least in part, and the p-type semiconductor region is in contact with the drift region and at least a portion of a rear surface of the channel region, a main electrode disposed on the surface layer and electrically connected to the contact region, a gate electrode disposed on the surface layer and extending from above a portion of the contact region to above at least a portion of the drift region via above the channel region, and an insulating layer covering at least the portion of the contact region and not covering at least the portion of the drift region. The gate electrode and the contact region are insulated by the insulating layer, and the gate electrode and the drift region are in direct contact to form a Schottky junction.
摘要翻译：半导体器件具有具有表面层和p型半导体区域的半导体衬底，其中表面层包括接触区域，沟道区域和漂移区域，沟道区域与接触区域相邻并与其接触，漂移区域与沟道区域相邻并且与沟道区域接触并且至少部分地包括n型杂质，并且p型半导体区域与漂移区域和沟道的后表面的至少一部分接触区域，设置在所述表面层上并电连接到所述接触区域的主电极，设置在所述表面层上并且从所述接触区域的一部分的上方延伸到所述漂移区域的至少一部分之上的栅电极，以及至少覆盖所述接触区域的部分并且至少覆盖所述漂移区域的部分的绝缘层。栅极电极和接触区域被绝缘层绝缘，栅电极和漂移区域直接接触形成肖特基结。

9. 发明申请

US20100038681A1 TRANSISTOR 有权
标题翻译：晶体管
公开(公告)号：US20100038681A1
公开(公告)日：2010-02-18
申请号：US12540230
申请日：2009-08-12
申请人： Masahiro SUGIMOTO , Tat-Sing Paul Chow , Zhongda Li , Totsu Kachi , Tsutomu Uesugi
发明人： Masahiro SUGIMOTO , Tat-Sing Paul Chow , Zhongda Li , Totsu Kachi , Tsutomu Uesugi
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/0642 , H01L29/1033 , H01L29/2003 , H01L29/4232 , H01L29/42368 , H01L29/66462 , H01L29/7788
摘要： An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.
摘要翻译：公开了一种HEMT型晶体管，其是常闭型，栅极阈值电压的变化小。晶体管设置有p型区域，势垒区域，绝缘膜，栅极电极。沟道区域连接到p型区域的上表面。通道区域是n型或i型，并且设置有第一通道区域和第二通道区域。阻挡区域与第一通道区域的上表面形成异质结。绝缘膜连接到第二通道区域的上表面和阻挡区域的上表面。栅电极经由绝缘膜面向第二沟道区和阻挡区。第一通道区域和第二通道区域在电流通路中串联布置。

10. 发明申请

US20080090395A1 Method for producing p-type group III nitride semiconductor and method for producing electrode for p-type group III nitride semiconductor 审中-公开
标题翻译： p型III族氮化物半导体的制造方法及p型III族氮化物半导体用电极的制造方法
公开(公告)号：US20080090395A1
公开(公告)日：2008-04-17
申请号：US11902087
申请日：2007-09-19
申请人： Masahiro Sugimoto , Masakazu Kanechika , Daigo Kikuta , Osamu Ishiguro , Tsutomu Uesugi , Tetsu Kachi
发明人： Masahiro Sugimoto , Masakazu Kanechika , Daigo Kikuta , Osamu Ishiguro , Tsutomu Uesugi , Tetsu Kachi
IPC分类号： H01L21/225
CPC分类号： H01L21/2258 , H01L21/28575 , H01L29/2003 , H01L29/452 , H01L29/7828 , H01L29/808 , H01L29/861 , H01L33/325
摘要： The present invention provides a p-type group III nitride semiconductor production method which is excellent in terms of reliability and reproducibility. A photoresist mask is formed on a surface of an n−-GaN layer. Subsequently, an Mg film is formed so as to cover the n−-GaN layer and the photoresist mask, and an Ni/Pt metal film is formed on the Mg film. Thereafter, the photoresist mask is removed, whereby the Mg film and the metal film remain only on a portion of the n−-GaN layer where a p-type region is formed. Subsequently, when thermal treatment is performed in an ammonia atmosphere at 900° C. for three hours, Mg is diffused in the n−-GaN layer while being activated. Therefore, a p-type region is formed. Thereafter, the Mg film and the metal film are removed by use of aqua regia.
摘要翻译：本发明提供了可靠性和再现性优异的p型III族氮化物半导体制造方法。光刻胶掩模形成在n + O-GaN层的表面上。随后，形成Mg膜，以覆盖n + SUP-GaN层和光致抗蚀剂掩模，并且在Mg膜上形成Ni / Pt金属膜。此后，除去光致抗蚀剂掩模，由此Mg膜和金属膜仅保留在形成p型区域的n + O - GaN层的一部分上。随后，当在900℃的氨气氛中进行3小时的热处理时，Mg在被激活的同时在n + SUP-GaN层中扩散。因此，形成p型区域。此后，通过使用王水去除Mg膜和金属膜。

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