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1. 发明申请

US20100013006A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100013006A1
公开(公告)日：2010-01-21
申请号：US12502251
申请日：2009-07-14
申请人： Masahiro SUGIMOTO , Tsutomu Uesugi , Masakazu Kanechika , Testsu Kachi
发明人： Masahiro SUGIMOTO , Tsutomu Uesugi , Masakazu Kanechika , Testsu Kachi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/8122 , H01L29/0623 , H01L29/0657 , H01L29/1029 , H01L29/1037 , H01L29/1075 , H01L29/1079 , H01L29/42316 , H01L29/7828 , H01L29/7832 , H01L29/7838 , H01L29/812
摘要： A semiconductor device has a semiconductor substrate having a surface layer and a p-type semiconductor region, wherein the surface layer includes a contact region, a channel region and a drift region, the channel region is adjacent to and in contact with the contact region, the drift region is adjacent to and in contact with the channel region and includes n-type impurities at least in part, and the p-type semiconductor region is in contact with the drift region and at least a portion of a rear surface of the channel region, a main electrode disposed on the surface layer and electrically connected to the contact region, a gate electrode disposed on the surface layer and extending from above a portion of the contact region to above at least a portion of the drift region via above the channel region, and an insulating layer covering at least the portion of the contact region and not covering at least the portion of the drift region. The gate electrode and the contact region are insulated by the insulating layer, and the gate electrode and the drift region are in direct contact to form a Schottky junction.
摘要翻译：半导体器件具有具有表面层和p型半导体区域的半导体衬底，其中表面层包括接触区域，沟道区域和漂移区域，沟道区域与接触区域相邻并与其接触，漂移区域与沟道区域相邻并且与沟道区域接触并且至少部分地包括n型杂质，并且p型半导体区域与漂移区域和沟道的后表面的至少一部分接触区域，设置在所述表面层上并电连接到所述接触区域的主电极，设置在所述表面层上并且从所述接触区域的一部分的上方延伸到所述漂移区域的至少一部分之上的栅电极，以及至少覆盖所述接触区域的部分并且至少覆盖所述漂移区域的部分的绝缘层。栅极电极和接触区域被绝缘层绝缘，栅电极和漂移区域直接接触形成肖特基结。

2. 发明申请

US20080090395A1 Method for producing p-type group III nitride semiconductor and method for producing electrode for p-type group III nitride semiconductor 审中-公开
标题翻译： p型III族氮化物半导体的制造方法及p型III族氮化物半导体用电极的制造方法
公开(公告)号：US20080090395A1
公开(公告)日：2008-04-17
申请号：US11902087
申请日：2007-09-19
申请人： Masahiro Sugimoto , Masakazu Kanechika , Daigo Kikuta , Osamu Ishiguro , Tsutomu Uesugi , Tetsu Kachi
发明人： Masahiro Sugimoto , Masakazu Kanechika , Daigo Kikuta , Osamu Ishiguro , Tsutomu Uesugi , Tetsu Kachi
IPC分类号： H01L21/225
CPC分类号： H01L21/2258 , H01L21/28575 , H01L29/2003 , H01L29/452 , H01L29/7828 , H01L29/808 , H01L29/861 , H01L33/325
摘要： The present invention provides a p-type group III nitride semiconductor production method which is excellent in terms of reliability and reproducibility. A photoresist mask is formed on a surface of an n−-GaN layer. Subsequently, an Mg film is formed so as to cover the n−-GaN layer and the photoresist mask, and an Ni/Pt metal film is formed on the Mg film. Thereafter, the photoresist mask is removed, whereby the Mg film and the metal film remain only on a portion of the n−-GaN layer where a p-type region is formed. Subsequently, when thermal treatment is performed in an ammonia atmosphere at 900° C. for three hours, Mg is diffused in the n−-GaN layer while being activated. Therefore, a p-type region is formed. Thereafter, the Mg film and the metal film are removed by use of aqua regia.
摘要翻译：本发明提供了可靠性和再现性优异的p型III族氮化物半导体制造方法。光刻胶掩模形成在n + O-GaN层的表面上。随后，形成Mg膜，以覆盖n + SUP-GaN层和光致抗蚀剂掩模，并且在Mg膜上形成Ni / Pt金属膜。此后，除去光致抗蚀剂掩模，由此Mg膜和金属膜仅保留在形成p型区域的n + O - GaN层的一部分上。随后，当在900℃的氨气氛中进行3小时的热处理时，Mg在被激活的同时在n + SUP-GaN层中扩散。因此，形成p型区域。此后，通过使用王水去除Mg膜和金属膜。

3. 发明授权

US08222675B2 Nitride semiconductor device including gate insulating portion containing AIN 有权
标题翻译：氮化物半导体器件包括含有AIN的栅极绝缘部分
公开(公告)号：US08222675B2
公开(公告)日：2012-07-17
申请号：US12544451
申请日：2009-08-20
申请人： Masahiro Sugimoto , Hiroyuki Ueda , Tsutomu Uesugi , Masakazu Kanechika , Tetsu Kachi
发明人： Masahiro Sugimoto , Hiroyuki Ueda , Tsutomu Uesugi , Masakazu Kanechika , Tetsu Kachi
IPC分类号： H01L29/778
CPC分类号： H01L29/2003 , H01L21/28264 , H01L29/41766 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/7787 , H01L29/7788
摘要： A nitride semiconductor device 2 comprises a nitride semiconductor layer 10. A gate insulating film 16 is formed on the surface of the nitride semiconductor layer 10. The gate insulating film 16 includes a portion composed of an aluminum nitride film 15 and a portion composed of an insulating material 14 that contains at least one of oxygen or silicon. A region W2 of the nitride semiconductor layer 10 facing the aluminum nitride film 15 is included in a region W1 of the nitride semiconductor layer 10 facing a gate electrode 18. The nitride semiconductor device 2 may further comprise a nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may be stacked on the surface of the nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may have a larger band gap than that of the nitride semiconductor lower layer 8 and have a heterojunction formed there between.
摘要翻译：氮化物半导体器件2包括氮化物半导体层10.栅极绝缘膜16形成在氮化物半导体层10的表面上。栅极绝缘膜16包括由氮化铝膜15构成的部分和由包含氧或硅中的至少一种的绝缘材料14。面向氮化铝膜15的氮化物半导体层10的区域W2包含在氮化物半导体层10的面向栅极电极18的区域W1中。氮化物半导体器件2还可以包括氮化物半导体下层8.氮化物半导体层半导体层10可以堆叠在氮化物半导体下层8的表面上。氮化物半导体层10可以具有比氮化物半导体下层8更大的带隙，并且在其间形成异质结。

4. 发明授权

US08110870B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08110870B2
公开(公告)日：2012-02-07
申请号：US12502251
申请日：2009-07-14
申请人： Masahiro Sugimoto , Tsutomu Uesugi , Masakazu Kanechika , Tetsu Kachi
发明人： Masahiro Sugimoto , Tsutomu Uesugi , Masakazu Kanechika , Tetsu Kachi
IPC分类号： H01L29/66
CPC分类号： H01L29/8122 , H01L29/0623 , H01L29/0657 , H01L29/1029 , H01L29/1037 , H01L29/1075 , H01L29/1079 , H01L29/42316 , H01L29/7828 , H01L29/7832 , H01L29/7838 , H01L29/812
摘要： A semiconductor device has a semiconductor substrate having a surface layer and a p-type semiconductor region, wherein the surface layer includes a contact region, a channel region and a drift region, the channel region is adjacent to and in contact with the contact region, the drift region is adjacent to and in contact with the channel region and includes n-type impurities at least in part, and the p-type semiconductor region is in contact with the drift region and at least a portion of a rear surface of the channel region, a main electrode disposed on the surface layer and electrically connected to the contact region, a gate electrode disposed on the surface layer and extending from above a portion of the contact region to above at least a portion of the drift region via above the channel region, and an insulating layer covering at least the portion of the contact region and not covering at least the portion of the drift region. The gate electrode and the contact region are insulated by the insulating layer, and the gate electrode and the drift region are in direct contact to form a Schottky junction.
摘要翻译：半导体器件具有具有表面层和p型半导体区域的半导体衬底，其中表面层包括接触区域，沟道区域和漂移区域，沟道区域与接触区域相邻并与其接触，漂移区域与沟道区域相邻并且与沟道区域接触并且至少部分地包括n型杂质，并且p型半导体区域与漂移区域和沟道的后表面的至少一部分接触区域，设置在所述表面层上并电连接到所述接触区域的主电极，设置在所述表面层上并且从所述接触区域的一部分的上方延伸到所述漂移区域的至少一部分之上的栅电极，以及至少覆盖所述接触区域的部分并且至少覆盖所述漂移区域的部分的绝缘层。栅极电极和接触区域被绝缘层绝缘，栅电极和漂移区域直接接触形成肖特基结。

5. 发明申请

US20100044753A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100044753A1
公开(公告)日：2010-02-25
申请号：US12544451
申请日：2009-08-20
申请人： Masahiro SUGIMOTO , Hiroyuki Ueda , Tsutomu Uesugi , Masakazu Kanechika , Tetsu Kachi
发明人： Masahiro SUGIMOTO , Hiroyuki Ueda , Tsutomu Uesugi , Masakazu Kanechika , Tetsu Kachi
IPC分类号： H01L29/205 , H01L29/78
CPC分类号： H01L29/2003 , H01L21/28264 , H01L29/41766 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/7787 , H01L29/7788
摘要： A nitride semiconductor device 2 comprises a nitride semiconductor layer 10. A gate insulating film 16 is formed on the surface of the nitride semiconductor layer 10. The gate insulating film 16 includes a portion composed of an aluminum nitride film 15 and a portion composed of an insulating material 14 that contains at least one of oxygen or silicon. A region W2 of the nitride semiconductor layer 10 facing the aluminum nitride film 15 is included in a region W1 of the nitride semiconductor layer 10 facing a gate electrode 18. The nitride semiconductor device 2 may further comprise a nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may be stacked on the surface of the nitride semiconductor lower layer 8. The nitride semiconductor layer 10 may have a larger band gap than that of the nitride semiconductor lower layer 8 and have a heterojunction formed there between.
摘要翻译：氮化物半导体器件2包括氮化物半导体层10.栅极绝缘膜16形成在氮化物半导体层10的表面上。栅极绝缘膜16包括由氮化铝膜15构成的部分和由包含氧或硅中的至少一种的绝缘材料14。面向氮化铝膜15的氮化物半导体层10的区域W2包含在氮化物半导体层10的面向栅极电极18的区域W1中。氮化物半导体器件2还可以包括氮化物半导体下层8.氮化物半导体层半导体层10可以堆叠在氮化物半导体下层8的表面上。氮化物半导体层10可以具有比氮化物半导体下层8更大的带隙，并且在其间形成异质结。

6. 发明授权

US06936484B2 Method of manufacturing semiconductor device and semiconductor device 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US06936484B2
公开(公告)日：2005-08-30
申请号：US10618085
申请日：2003-07-14
申请人： Masakazu Kanechika , Kenji Nakashima , Yasuichi Mitsushima , Tetsu Kachi
发明人： Masakazu Kanechika , Kenji Nakashima , Yasuichi Mitsushima , Tetsu Kachi
IPC分类号： H01L21/265 , H01L21/3065 , H01L21/308 , H01L21/335 , H01L21/8242 , H01L29/06 , H01L29/76 , H01L29/788 , H01L21/00
CPC分类号： H01L21/26506 , H01L21/26566 , H01L21/3065 , H01L21/3086 , H01L27/10864 , H01L29/0657 , H01L29/66439 , H01L29/7613 , H01L29/7888
摘要： An impurity precipitation region is formed by introducing an impurity, e.g., oxygen, into a silicon substrate or a silicon layer and thermally treating it, and performing high selectivity anisotropic etching with the precipitation region used as a micro mask. Thus, a cone (conic body or truncated conic body having an annular leading end) having a very sharp and slender needle shape with an aspect ratio of about 10 and a diameter of about 10 nm to 30 nm in the vicinity of its leading end is obtained with the micro mask used as the top. By forming an insulation layer and a drive electrode such as a gate electrode around the cone, the cone can be used for a field emission device, a single electron transistor, a memory device, a high frequency switching device, a probe of a scanning type microscope or the like.
摘要翻译：通过将诸如氧的杂质引入到硅衬底或硅层中并对其进行热处理并且使用用作微掩模的沉淀区进行高选择性各向异性蚀刻来形成杂质析出区。因此，在其前端附近具有纵横比为约10和直径约10nm至30nm的非常锋利且细长的针形的锥体（圆锥体或具有环形前端的截头圆锥体）用微型掩模作为顶部获得。通过在锥体周围形成绝缘层和诸如栅电极的驱动电极，锥体可用于场致发射器件，单电子晶体管，存储器件，高频开关器件，扫描型探针显微镜等。

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