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1. 发明专利

JP2007227819A Method of manufacturing electronic component 有权
标题翻译：制造电子元件的方法
公开(公告)号：JP2007227819A
公开(公告)日：2007-09-06
申请号：JP2006049523
申请日：2006-02-27
申请人： Toshiba Corp , 株式会社東芝
发明人： TOYODA HIROSHI , HASUNUMA MASAHIKO
IPC分类号： H01L21/288 , C25D7/12 , C25D21/12 , H01L21/28 , H01L21/3205 , H01L23/52
CPC分类号： H01L21/2885 , C25D5/34 , C25D7/123 , H01L21/76829 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76877
摘要： PROBLEM TO BE SOLVED: To provide a method for reducing occurrence of non-deposition or defect of a plating film after electrolytic plating by suppressing the dissolution of a seed film.
SOLUTION: A method of manufacturing an electronic component includes: a seed film forming step (S110) of forming a seed film on a substrate; a cooling step (S112) of cooling the seed film; and a plating step (S114) of immersing the cooled seed film in a plating liquid, and performing electrolytic plating using the seed film as a cathode.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种通过抑制种子膜的溶解来减少电解镀覆后的镀膜的不沉积或缺陷的发生的方法。解决方案：一种电子部件的制造方法，包括：在基板上形成种子膜的种子膜形成工序（S110）冷却种子膜的冷却步骤（S112）以及将冷却后的种子膜浸渍在电镀液中的电镀工序（S114），使用种子膜进行电解电镀作为阴极。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2005307311A Substrate treatment device and substrate treatment method 审中-公开
标题翻译：基板处理装置和基板处理方法
公开(公告)号：JP2005307311A
公开(公告)日：2005-11-04
申请号：JP2004128778
申请日：2004-04-23
申请人： Ebara Corp , Toshiba Corp , 株式会社東芝 , 株式会社荏原製作所
发明人： MISHIMA KOJI , SUZUKI HIDENAO , NOMURA KAZUFUMI , KANEKO HISAFUMI , TOYODA HIROSHI
IPC分类号： C23C18/18 , C23C18/16 , C23F1/00 , C23F1/08 , C23G3/02 , C25D5/34 , C25D7/12 , C25D17/00 , C25D21/12 , C25F3/12 , C25F3/30 , C25F7/00 , H01L21/00 , H01L21/02 , H01L21/304 , H01L21/306 , H01L21/3063
CPC分类号： H01L21/02063 , C23C18/1632 , C23F1/08 , C23G3/027 , C25D5/34 , C25D17/00 , C25D21/12 , C25F7/00 , H01L21/02074 , H01L21/67173 , H01L21/6723
摘要： PROBLEM TO BE SOLVED: To suppress the defect in a process caused by static electricity in the surface of a substrate by suitably controlling the electrified state of the substrate in accordance with the kind of a wet process. SOLUTION: The substrate treatment device comprises a static electricity control part 30 of controlling the static electricity in a substrate and a wet treatment apparatus of performing wet treatment to the substrate in which the static electricity has been controlled. The static electricity control part, e.g., comprises a static electricity sensor 32 for detecting the electrified state of the substrate and an electrified part blower 38, and removes the static electricity electrified to the substrate or electrifies the substrate to an optional electrified state. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过根据湿法的种类适当地控制基板的通电状态来抑制基板表面中的由静电产生的处理中的缺陷。解决方案：基板处理装置包括控制基板中的静电的静电控制部30和对已经控制静电的基板进行湿处理的湿式处理装置。静电控制部件例如包括用于检测基板的通电状态的静电传感器32和带电部鼓风机38，并且去除对基板通电的静电或使基板通电至可选择的通电状态。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005133160A Substrate treatment device and method 审中-公开
标题翻译：基板处理装置和方法
公开(公告)号：JP2005133160A
公开(公告)日：2005-05-26
申请号：JP2003371319
申请日：2003-10-30
申请人： Ebara Corp , Toshiba Corp , 株式会社東芝 , 株式会社荏原製作所
发明人： SUZUKI HIDENAO , MISHIMA KOJI , KANDA HIROYUKI , NOMURA KAZUFUMI , IDE KUNIHITO , YAHIRO KAZUYUKI , TOYODA HIROSHI , MATSUDA TETSURO
IPC分类号： C25D7/12 , C25D17/00 , C25D17/06 , C25D21/10 , H01L21/288 , H01L21/3205 , H01L21/68 , H01L21/683
CPC分类号： H01L21/2885 , C25D7/123 , C25D17/001 , C25D17/06
摘要： PROBLEM TO BE SOLVED: To prevent the generation of defects caused by microbubbles, particles or the like slightly present in an electrolytic solution such as a plating liquid, and to improve the yield. SOLUTION: The substrate treatment device comprises: a substrate holding part 14 holding a substrate W; a first electrode 20 contacted with the substrate W and energizing the face to be treated in the substrate W; a second electrode 42 arranged at the position confronted with the face to be treated in the substrate held by the substrate holding part 14; and an electrolytic solution injection means 44 injecting an electrolytic solution 26 inside a region held between the face to be treated in the substrate held by the substrate holding part 14 and the second electrode 42. The substrate holding part 14 rotates the substrate W while repeating acceleration or deceleration and/or normal rotation or reverse rotation under electrolytic treatment. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止微电解产生的缺陷，微电解液等电解液中存在的微粒等，提高产率。基板处理装置包括：保持基板W的基板保持部14; 第一电极20与基板W接触并对基板W中待处理的面进行激励; 第二电极42，其布置在与由待保护的基板保持部分14保持的基板中的被处理面相对的位置; 以及电解液注入装置44，其在保持在由基板保持部分14保持的基板中的被处理面之间的区域内注入电解液26和第二电极42.基板保持部14在重复加速的同时旋转基板W 或在电解处理下减速和/或正常旋转或反向旋转。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2005042158A Method and apparatus for plating 审中-公开
标题翻译：用于镀层的方法和装置
公开(公告)号：JP2005042158A
公开(公告)日：2005-02-17
申请号：JP2003202515
申请日：2003-07-28
申请人： Ebara Corp , Toshiba Corp , 株式会社東芝 , 株式会社荏原製作所
发明人： KURASHINA KEIICHI , NAMIKI KEISUKE , NAKADA TSUTOMU , MISHIMA KOJI , TOYODA HIROSHI , MATSUDA TETSURO , KANEKO HISAFUMI
IPC分类号： C25D7/00 , C25D17/00 , H01L21/288 , H01L21/60
CPC分类号： H01L21/2885 , H01L21/76879
摘要： PROBLEM TO BE SOLVED: To provide a plating method for selectively depositing a metal plating film like a copper film on the inner part of a recess in an electric wiring such as a groove or micro pore in electric wiring for a circuit. SOLUTION: The electroplating method for filling the wiring material 50 into the fine recesses 42 and 44 for the electric wiring, by forming a seed layer 48 on a substrate W having the fine recesses 42 and 44, and plating a metal on the seed layer 48 through applying an electric current between the seed layer 48 and an anode 28 while filling a plating solution 20 in between them, includes contacting or approaching a diaphragm 34 with or to the seed layer 48, which inhibits metal ions from permeating therethrough without inhibiting hydrogen ions in the plating solution from permeating therethrough. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种电镀方法，用于在用于电路的电线中的诸如凹槽或微孔的电布线的凹部的内部部分上选择性地沉积诸如铜膜的金属镀膜。解决方案：通过在具有细凹部42和44的基板W上形成种子层48，并在金属层上镀金属的方法，用于将布线材料50填充到用于电布线的细凹槽42和44中的电镀方法晶种层48通过在种子层48和阳极28之间施加电流而同时填充它们之间的电镀溶液20，包括使隔膜34接触或接近种子层48，其阻止金属离子渗入其中而不通过其中抑制电镀溶液中的氢离子渗透通过。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2013194305A Plating apparatus and plating method 审中-公开
标题翻译：电镀设备和电镀方法
公开(公告)号：JP2013194305A
公开(公告)日：2013-09-30
申请号：JP2012065380
申请日：2012-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： MORITA TOSHIYUKI , IKEGAYA FUMITOSHI , TOYODA HIROSHI
IPC分类号： C25D5/08 , C25D7/12 , H01L21/288
摘要： PROBLEM TO BE SOLVED: To provide a plating apparatus capable of suppressing deterioration in in-plane uniformity, and to provide a method of the plating apparatus.SOLUTION: A plating apparatus includes: a plating tank; an anode; an adjusting member; and a reversing mechanism. The plating tank is fed with a plating liquid. The anode is arranged at the inside of the plating tank. The adjusting member is arranged at the inside of the plating tank and adjusts an electric field between the anode and a cathode to form into the substrate to be plated. The reversing mechanism reverses the flow of a plating liquid in the plating tank.
摘要翻译：要解决的问题：提供一种能够抑制面内均匀性劣化的电镀装置，并提供电镀装置的方法。电镀装置包括：电镀槽; 阳极; 调节构件; 和倒车机制。电镀槽中装有电镀液。阳极布置在镀槽内部。调整部件配置在镀槽内部，调整阳极和阴极之间的电场，形成被镀基板。反转机构使镀槽中的镀液的流动反转。

6. 发明专利

JP2008112772A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2008112772A
公开(公告)日：2008-05-15
申请号：JP2006293488
申请日：2006-10-30
申请人： Toshiba Corp , 株式会社東芝
发明人： HASUNUMA MASAHIKO , KANEKO HISAFUMI , TOYODA HIROSHI
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/76877 , C23C26/00 , C25D5/02 , C25D5/18 , C25D5/50 , C25D7/123 , H01L21/2885
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of improving reliability in wiring. SOLUTION: The method of manufacturing a semiconductor device is provided. The method comprises: a process of forming a plating film 4, which is embedded in at least a first layer wiring channel 1a and has higher impurity concentration at an upper portion 4a than a lower portion 4b, on a wafer W having the first layer wiring channel 1a on a surface; a process of heat-treating the plating film 4; and a process of removing the plating film 4 at a portion except a portion embedded in the first layer wiring channel 1a after heat-treating the plating film 4. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够提高布线可靠性的半导体器件的制造方法。解决方案：提供制造半导体器件的方法。该方法包括：在具有第一层布线的晶片W上形成电镀膜4的工艺，该镀膜4嵌入至少第一层布线通道1a中，并且在比上部4b的上部4a具有更高的杂质浓度表面上的通道1a; 对镀膜4进行热处理的工序; 以及在对镀膜4进行热处理之后除去嵌入第一层布线通道1a中的部分之外的部分去除镀膜4的过程。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2006100698A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2006100698A
公开(公告)日：2006-04-13
申请号：JP2004287089
申请日：2004-09-30
申请人： Toshiba Corp , 株式会社東芝
发明人： TOYODA HIROSHI , ITO SACHIYO , HASUNUMA MASAHIKO , KANEKO HISAFUMI
IPC分类号： H01L21/3205 , C23C14/16
CPC分类号： H01L21/76838 , C23C14/0635 , C23C14/165
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for reducing a void in wiring in a recess, and for securing the reliability of wiring.
SOLUTION: A compression stress force application film 5 constituted of substances having the coefficients of thermal expansion which are 60% or less to the coefficients of thermal expansion of metal configuring a plating film 4 is formed on the plating film 4, and heat treatment is carried out while a compression stress is applied to the plating film 4 by a compression stress applying film 5.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于制造半导体器件的方法，用于减小凹部中布线的空隙，并确保布线的可靠性。解决方案：在镀膜4上形成由热膨胀系数为60％以下的构成电镀膜4的金属的热膨胀系数构成的压应力施加膜5，在通过压缩应力膜5对镀膜4施加压缩应力的同时进行处理。（C）2006，JPO＆NCIPI

8. 发明专利

JP2005223059A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005223059A
公开(公告)日：2005-08-18
申请号：JP2004028098
申请日：2004-02-04
申请人： Toshiba Corp , 株式会社東芝
发明人： HASUNUMA MASAHIKO , TOYODA HIROSHI , YAHIRO KAZUYUKI
IPC分类号： H01L21/3205 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with a copper wiring inhibiting the shortening of a lifetime due to an EM fault and an SM fault and having a high reliability.
SOLUTION: The semiconductor device has a wiring layer composed of copper or a copper alloy containing oxygen and chlorine in a mean concentration of 1.0×10
16 to 2.0×10
18 atoms/cm
3 respectively.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供具有铜布线的半导体器件，其阻止由于EM故障和SM故障而缩短一段时间并具有高可靠性。解决方案：半导体器件具有由铜或含有氧和氯的铜合金构成的布线层，平均浓度为1.0×10 16 至2.0×10 18 原子/ cm 3 。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2010186977A Method for fabricating semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2010186977A
公开(公告)日：2010-08-26
申请号：JP2009130831
申请日：2009-05-29
申请人： Toshiba Corp , 株式会社東芝
发明人： HAYASHI HIROMI , SAKATA ATSUKO , WATANABE KATSURA , MATSUNAGA NORIAKI , NAKAO SHINICHI , WADA MAKOTO , TOYODA HIROSHI
IPC分类号： H01L21/3205 , H01L23/52
CPC分类号： H01L23/485 , H01L21/76814 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76867 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for improving an EM characteristic while suppressing increase of wiring resistance, and to provide a method for fabricating the same. SOLUTION: This method for fabricating the semiconductor device includes: a process (S104) of forming an insulation film on a substrate; a process (S106) of forming an opening on the insulation film; a process (S108) of forming, in the opening, a metal-containing film having silicide-forming energy smaller than Cu silicide-forming energy; a process (S112) of embedding a copper (Cu) film in the opening with the metal-containing film formed therein; and a process (S120) of selectively forming, on the Cu film, a compound film containing Cu and Si at a temperature below 300°C. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种用于提高EM特性的半导体器件，同时抑制布线电阻的增加，并提供其制造方法。解决方案：用于制造半导体器件的方法包括：在衬底上形成绝缘膜的工艺（S104）; 在绝缘膜上形成开口的工序（S106）在开口中形成具有比形成硅化硅的能量小的硅化物形成能的含金属膜的工序（S108）在其中形成有含金属膜的开口中嵌入铜（Cu）膜的工序（S112）以及在Cu膜上选择性地在低于300℃的温度下形成含有Cu和Si的化合物膜的工艺（S120）。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2008053753A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2008053753A
公开(公告)日：2008-03-06
申请号：JP2007291015
申请日：2007-11-08
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDA TETSURO , TOYODA HIROSHI , KANEKO HISAFUMI
IPC分类号： H01L21/3205 , H01L23/52
CPC分类号： C23C18/1653
摘要： PROBLEM TO BE SOLVED: To form a Cu film with an excellent buried shape in an interior of a wiring groove and a connecting hole by electrolysis plating.
SOLUTION: A method for manufacturing a semiconductor device has: a step of forming an insulating film 11 on a semiconductor substrate; a step of forming a buried region 12 for at least one of the wiring groove and the connecting hole in the insulating film 11; a step of forming a conductive amorphous film 15 on the buried region 12, with a thickness that the interior of the buried region 12 is not buried; and a step of forming a conductive film 16 on the amorphous film 15, with a thickness that the interior of the buried region 12 is buried by plating.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过电解电镀在布线槽和连接孔的内部形成具有优良掩埋形状的Cu膜。解决方案：半导体器件的制造方法具有：在半导体衬底上形成绝缘膜11的步骤; 在绝缘膜11中形成布线槽和连接孔中的至少一个的掩埋区域12的工序; 在掩埋区域12上形成导电非晶膜15的步骤，其中埋入区域12的内部未被埋置; 以及在非晶膜15上形成导电膜16的步骤，其厚度通过电镀掩埋埋入区域12的内部。版权所有（C）2008，JPO＆INPIT

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