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1. 发明授权

US5426745A Apparatus including a pair of neural networks having disparate functions cooperating to perform instruction recognition 失效
标题翻译：装置包括具有不同功能的一对神经网络，协同执行指令识别
公开(公告)号：US5426745A
公开(公告)日：1995-06-20
申请号：US206195
申请日：1994-03-03
申请人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
发明人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
IPC分类号： G06F15/18 , G06F3/00 , G06F3/16 , G06F15/00 , G06F15/02 , G06K9/52 , G06N3/00 , G06N99/00 , G07C9/00 , G10L15/06 , G10L15/16
CPC分类号： G10L15/16 , G06F3/16 , G06K9/522 , G07C9/00071 , G06K2209/01
摘要： There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks respectively provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.
摘要翻译：提供了能够响应于操作者特有的输入数据而操作的定制个人终端装置，包括用于识别输入的语音的语音识别单元，用于识别输入的图像的图像识别单元，以及用于识别输入的指令的指令识别单元。分别设置在语音，图像和指令识别单元中的至少两个中的神经网络，可操作地连接到各个识别单元的总线，可操作地连接到总线以对语音进行处理的处理器，以及通过识别识别的图像和指令单位。此外，存储器可操作地连接到总线，并且控制单元在处理器的控制下对各个识别单元和存储器之间的信息交换进行控制。

2. 发明授权

US5163111A Customized personal terminal device 失效
标题翻译：定制个人终端设备
公开(公告)号：US5163111A
公开(公告)日：1992-11-10
申请号：US567010
申请日：1990-08-14
申请人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
发明人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
IPC分类号： G06F15/18 , G06F3/00 , G06F3/16 , G06F15/00 , G06F15/02 , G06K9/52 , G06N3/00 , G06N99/00 , G07C9/00 , G10L15/06 , G10L15/16
CPC分类号： G10L15/16 , G06F3/16 , G06K9/522 , G07C9/00071 , G06K2209/01
摘要： There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks are provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.
摘要翻译：提供了能够响应于操作者特有的输入数据而操作的定制个人终端装置，包括用于识别输入的语音的语音识别单元，用于识别输入的图像的图像识别单元，以及用于识别输入的指令的指令识别单元。神经网络提供在语音，图像和指令识别单元中的至少两个中，可操作地连接到各个识别单元的总线，可操作地连接到总线以对语音执行处理的处理器，以及通过识别识别的图像和指令单位。此外，存储器可操作地连接到总线，并且控制单元在处理器的控制下对各个识别单元和存储器之间的信息交换进行控制。

3. 发明授权

US06993597B2 Terminal apparatus 失效
标题翻译：终端设备
公开(公告)号：US06993597B2
公开(公告)日：2006-01-31
申请号：US10639445
申请日：2003-08-13
申请人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
发明人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
IPC分类号： G06F3/00
CPC分类号： G06F9/3885 , G06F1/3203 , G06F15/7807
摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.
摘要翻译：低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。此外，DSP和CPU的数据输入和输出需要两个外设单元。因此，DSP和CPU之间会发生无关的通信开销。本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

4. 发明授权

US5027400A Multimedia bidirectional broadcast system 失效
标题翻译：多媒体双向广播系统
公开(公告)号：US5027400A
公开(公告)日：1991-06-25
申请号：US394786
申请日：1989-08-16
申请人： Toru Baji , Yukio Nakano , Shiro Tanabe , Tetsuya Nakagawa , Hirotsugu Kojima
发明人： Toru Baji , Yukio Nakano , Shiro Tanabe , Tetsuya Nakagawa , Hirotsugu Kojima
IPC分类号： G06F17/30 , G09F27/00 , H04H9/00 , H04H20/28 , H04H20/76 , H04H60/31 , H04L12/00 , H04N7/16 , H04N7/173 , H04Q11/04
CPC分类号： H04H60/31 , G09F27/00 , H04H20/28 , H04H20/76 , H04N21/2543 , H04N21/4722 , H04N21/812 , H04N7/173 , H04N7/17336 , H04Q11/0478 , H04L2012/5638
摘要： A multimedia bidirectional broadcast system including a broadcast station and subscriber terminals. The broadcast station includes a main control unit having therein a data base control table in which program and commerical down load sequences are recorded depending on a setting effected by a subscriber, a motion picture program data base, a commerical data base, a program transmitter for effecting accesses and transmissions of transmission programs onto transmission lines based on the setting of the main control unit, a commercial transmitter for accessing the commerical data base and for transmitting content thereof based on the setting of the main control unit, an image encoder for achieving a bandwidth compression on a video signal, a cell assembler for processing data to be transmitted onto a broadband transmission line so as to generate a cell of the data, and an asynchronous transfer mode exchange for delivering the cell to a subscriber system associated therewith. Each of the subscriber systems includes a network terminal, a terminal control unit, a decoder to decode the compressed video signal, and a television monitor.

5. 发明授权

US06353863B1 Terminal 有权
标题翻译：终奌站
公开(公告)号：US06353863B1
公开(公告)日：2002-03-05
申请号：US09051286
申请日：1998-12-01
申请人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
发明人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
IPC分类号： G06F300
CPC分类号： G06F9/3885 , G06F1/3203 , G06F15/7807
摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.
摘要翻译：低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。此外，DSP和CPU的数据输入和输出需要两个外设单元。因此，DSP和CPU之间会发生无关的通信开销。本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

6. 发明申请

US20060085563A1 Terminal apparatus 审中-公开
公开(公告)号：US20060085563A1
公开(公告)日：2006-04-20
申请号：US11289389
申请日：2005-11-30
申请人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
发明人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
IPC分类号： G06F3/00
CPC分类号： G06F9/3885 , G06F1/3203 , G06F15/7807
摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

7. 发明授权

US06643713B2 Apparatus has a microprocessor including DSP and a CPU integrated with each other as a single bus master 有权
标题翻译：装置具有包括DSP和CPU的微处理器，它们作为单总线主机彼此集成
公开(公告)号：US06643713B2
公开(公告)日：2003-11-04
申请号：US10028425
申请日：2001-12-28
申请人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
发明人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
IPC分类号： G06F300
CPC分类号： G06F9/3885 , G06F1/3203 , G06F15/7807
摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.
摘要翻译：低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。此外，DSP和CPU的数据输入和输出需要两个外设单元。因此，DSP和CPU之间会发生无关的通信开销。本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

8. 发明授权

US5638524A Digital signal processor and method for executing DSP and RISC class instructions defining identical data processing or data transfer operations 失效
标题翻译：用于执行DSP和RISC类指令的数字信号处理器和方法，用于定义相同的数据处理或数据传输操作
公开(公告)号：US5638524A
公开(公告)日：1997-06-10
申请号：US443199
申请日：1995-05-17
申请人： Atsushi Kiuchi , Toru Baji , Tetsuya Nakagawa , Kenji Kaneko
发明人： Atsushi Kiuchi , Toru Baji , Tetsuya Nakagawa , Kenji Kaneko
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3822
摘要： A digital signal processor that includes an instruction memory, a program control unit, and an instruction decoder. The instruction memory stores a sequence of instruction words including DSP instruction words and RISC instruction words. The program control unit outputs an instruction address to the instruction memory so as to select one instruction word in the instruction memory. Every DSP instruction word identifies one data processing operation and one data transfer operation to be performed. The DSP instruction words include a predefined DSP instruction word having separate source and destination fields for specifying register locations for data sources and data destinations. The RISC instruction words include a predefined RISC instruction word corresponding to the predefined DSP instruction word. The predefined RISC instruction word has separate source and destination fields for specifying register locations for data sources and data destinations. One of the source and destination fields in the predefined RISC instruction word has more bits than the corresponding field in the predefined DSP instruction word. The instruction decoder decodes the selected instruction.
摘要翻译：一种包括指令存储器，程序控制单元和指令译码器的数字信号处理器。指令存储器存储包括DSP指令字和RISC指令字的指令字序列。程序控制单元向指令存储器输出指令地址，以便在指令存储器中选择一个指令字。每个DSP指令字标识要执行的一个数据处理操作和一个数据传送操作。 DSP指令字包括具有用于指定数据源和数据目的地的寄存器位置的独立源和目的地字段的预定义DSP指令字。 RISC指令字包括与预定义的DSP指令字对应的预定RISC指令字。预定义的RISC指令字具有用于指定数据源和数据目的地的寄存器位置的单独的源和目标字段。预定义RISC指令字中的源和目标字段之一具有比预定义DSP指令字中相应字段更多的位。指令译码器解码所选择的指令。

9. 发明授权

US08090398B2 Terminal apparatus 有权
标题翻译：终端设备
公开(公告)号：US08090398B2
公开(公告)日：2012-01-03
申请号：US12112968
申请日：2008-04-30
申请人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
发明人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
IPC分类号： H04M1/00
CPC分类号： G06F9/3885 , G06F1/3203 , G06F15/7807
摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.
摘要翻译：低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。此外，DSP和CPU的数据输入和输出需要两个外设单元。因此，DSP和CPU之间会发生无关的通信开销。本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

10. 发明授权

US5241679A Data processor for executing data saving and restoration register and data saving stack with corresponding stack storage for each register 失效
标题翻译：用于执行数据保存和恢复寄存器和数据保存堆栈的数据处理器，每个寄存器具有相应的堆栈存储
公开(公告)号：US5241679A
公开(公告)日：1993-08-31
申请号：US545290
申请日：1990-06-27
申请人： Tetsuya Nakagawa , Masafumi Miyamoto , Yasuhiro Sagesaka , Toru Baji
发明人： Tetsuya Nakagawa , Masafumi Miyamoto , Yasuhiro Sagesaka , Toru Baji
IPC分类号： G06F9/42 , G06F9/30 , G06F9/46 , G06F9/48
CPC分类号： G06F9/3004
摘要： A data processor comprises a plurality of registers 1 (registers a to d), a plurality of data saving stack memory devices 2 coupled to the registers 1 for exclusive use thereof, respectively, and an instruction decoder for decoding instructions for controlling the registers 1 and the data saving stack memory devices 2 in accordance with the result of the instruction decoding. In response to an instruction "PUSH", the contents of the registers 1 (registers a to d) are selectively saved to the data saving stack memory device 2. In response to a instruction "POP", the contents of the data saving stack memory devices 2 are selectively restored to the registers 1 (registers a to d). Each of the instructions "PUSH" and "POP" has a field for indicating need or needlessness of the saving and restoration for each of the registers 1 and each of the data saving memories 2.
摘要翻译：数据处理器包括多个寄存器1（寄存器a至d），分别耦合到其专用寄存器1的多个数据保存堆存储器件2和用于解码用于控制寄存器1和1的指令的指令译码器数据保存堆栈存储器件2根据指令译码的结果。响应于“PUSH”指令，将寄存器1（寄存器a至d）的内容选择性地保存到数据保存堆存储器件2.响应于指令“POP”，数据保存堆栈存储器的内容设备2被选择性地恢复到寄存器1（寄存器a到d）。每个指令“PUSH”和“POP”具有用于指示每个寄存器1和每个数据保存存储器2的保存和恢复的需要或不必要的字段。

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