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1. 发明授权

US5426745A Apparatus including a pair of neural networks having disparate functions cooperating to perform instruction recognition 失效
标题翻译：装置包括具有不同功能的一对神经网络，协同执行指令识别
公开(公告)号：US5426745A
公开(公告)日：1995-06-20
申请号：US206195
申请日：1994-03-03
申请人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
发明人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
IPC分类号： G06F15/18 , G06F3/00 , G06F3/16 , G06F15/00 , G06F15/02 , G06K9/52 , G06N3/00 , G06N99/00 , G07C9/00 , G10L15/06 , G10L15/16
CPC分类号： G10L15/16 , G06F3/16 , G06K9/522 , G07C9/00071 , G06K2209/01
摘要： There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks respectively provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.
摘要翻译：提供了能够响应于操作者特有的输入数据而操作的定制个人终端装置，包括用于识别输入的语音的语音识别单元，用于识别输入的图像的图像识别单元，以及用于识别输入的指令的指令识别单元。分别设置在语音，图像和指令识别单元中的至少两个中的神经网络，可操作地连接到各个识别单元的总线，可操作地连接到总线以对语音进行处理的处理器，以及通过识别识别的图像和指令单位。此外，存储器可操作地连接到总线，并且控制单元在处理器的控制下对各个识别单元和存储器之间的信息交换进行控制。

2. 发明授权

US5163111A Customized personal terminal device 失效
标题翻译：定制个人终端设备
公开(公告)号：US5163111A
公开(公告)日：1992-11-10
申请号：US567010
申请日：1990-08-14
申请人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
发明人： Toru Baji , Kouki Noguchi , Tetsuya Nakagawa , Motonobu Tonomura , Hajime Akimoto , Toshiaki Masuhara
IPC分类号： G06F15/18 , G06F3/00 , G06F3/16 , G06F15/00 , G06F15/02 , G06K9/52 , G06N3/00 , G06N99/00 , G07C9/00 , G10L15/06 , G10L15/16
CPC分类号： G10L15/16 , G06F3/16 , G06K9/522 , G07C9/00071 , G06K2209/01
摘要： There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks are provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.
摘要翻译：提供了能够响应于操作者特有的输入数据而操作的定制个人终端装置，包括用于识别输入的语音的语音识别单元，用于识别输入的图像的图像识别单元，以及用于识别输入的指令的指令识别单元。神经网络提供在语音，图像和指令识别单元中的至少两个中，可操作地连接到各个识别单元的总线，可操作地连接到总线以对语音执行处理的处理器，以及通过识别识别的图像和指令单位。此外，存储器可操作地连接到总线，并且控制单元在处理器的控制下对各个识别单元和存储器之间的信息交换进行控制。

3. 发明授权

US4935901A Semiconductor memory with divided bit load and data bus lines 失效
公开(公告)号：US4935901A
公开(公告)日：1990-06-19
申请号：US158259
申请日：1988-02-19
申请人： Toshio Sasaki , Osamu Minato , Shigeru Honjiyo , Koichiro Ishibashi , Toshiaki Masuhara
发明人： Toshio Sasaki , Osamu Minato , Shigeru Honjiyo , Koichiro Ishibashi , Toshiaki Masuhara
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).

4. 发明授权

US4710648A Semiconductor including signal processor and transient detector for low temperature operation 失效
标题翻译：半导体包括用于低温操作的信号处理器和瞬态检测器
公开(公告)号：US4710648A
公开(公告)日：1987-12-01
申请号：US731014
申请日：1985-05-06
申请人： Shoji Hanamura , Masaaki Aoki , Toshiaki Masuhara
发明人： Shoji Hanamura , Masaaki Aoki , Toshiaki Masuhara
IPC分类号： G11C8/18 , H01L27/092 , H01L27/105 , H01L27/108 , H03K5/1534 , H03K19/00 , H03K17/16 , H03K19/20
CPC分类号： H03K5/1534 , G11C8/18 , H01L27/092 , H01L27/10805 , H03K19/0016 , H01L27/105
摘要： Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized.
摘要翻译：响应于信号处理开始信号，电荷被提供给处于信号处理器内的电荷存储状态的电路节点。处理器在低温范围内操作，例如在温度低于200K的范围内。通过这种结构，泄漏电流减小，可以获得与动态电路相当的高度积分，并且可以实现不需要任何复杂的内部/外部定时信号的静态电路的简单性。

5. 发明授权

US4581628A Circuit programming by use of an electrically conductive light shield 失效
标题翻译：使用导电灯罩进行电路编程
公开(公告)号：US4581628A
公开(公告)日：1986-04-08
申请号：US424370
申请日：1982-09-27
申请人： Tateoki Miyauchi , Mikio Hongo , Masao Mitani , Isao Tanabe , Toshiaki Masuhara
发明人： Tateoki Miyauchi , Mikio Hongo , Masao Mitani , Isao Tanabe , Toshiaki Masuhara
IPC分类号： H01L21/3205 , H01L21/00 , H01L21/82 , H01L23/52 , H01L23/525 , H01L23/552 , H01L27/10 , H01L23/48 , H01L29/04
CPC分类号： H01L21/82 , H01L23/525 , H01L23/5254 , H01L23/552 , H01L2924/0002
摘要： The present invention consists in a semiconductor integrated circuit device characterized in that a circuit programming wiring layer is formed on an insulating film which is provided on a semiconductor substrate, and that a light shielding protective mask material is deposited around the circuit programming wiring layer except a program part thereof, through an insulating film.
摘要翻译：本发明是一种半导体集成电路器件，其特征在于，在设置在半导体衬底上的绝缘膜上形成电路编程布线层，并且在电路编程布线层周围沉积遮光保护掩模材料，除了程序部分，通过绝缘膜。

6. 发明授权

US4539660A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4539660A
公开(公告)日：1985-09-03
申请号：US331278
申请日：1981-12-16
申请人： Katsuki Miyauchi , Tetsuichi Kudo , Osamu Minato , Toshiaki Masuhara , Yoshio Uetani
发明人： Katsuki Miyauchi , Tetsuichi Kudo , Osamu Minato , Toshiaki Masuhara , Yoshio Uetani
IPC分类号： H02J7/00 , G06F1/00 , G06F1/26 , G06F12/16 , G11C5/14 , G11C11/413 , H01B5/14 , H01L21/336 , H01L21/8247 , H01L23/495 , H01L25/00 , H01L27/105 , H01L29/788 , H01L29/792 , H01M2/10 , H01M4/58 , H01M10/052 , H01M10/0562 , H01M10/44 , H02J1/00 , H02J7/34 , G11C11/34
CPC分类号： H01M10/0562 , G11C5/141 , H01L23/49593 , H01M2/1066 , H01L2224/49171 , H01L24/49 , H01L2924/00014 , H01L2924/01014 , H01L2924/10253 , H01L2924/14 , H01L2924/19041
摘要： A nonvolatile memory in which at least one power supply element is carried with an integrated circuit chip containing the memory and connected to power supply terminals of the integrated circuit chip having a memory cell array in which a plurality of memory elements or memory circuits are arrayed.
摘要翻译：一种非易失性存储器，其中至少一个电源元件被携带有集成电路芯片，所述集成电路芯片包含所述存储器并且连接到所述集成电路芯片的电源端子，所述集成电路芯片具有其中排列有多个存储器元件或存储器电路的存储单元阵列。

7. 发明授权

US4089022A Electron device 失效
标题翻译：电子器件
公开(公告)号：US4089022A
公开(公告)日：1978-05-09
申请号：US744864
申请日：1976-11-24
申请人： Shojiro Asai , Toshiaki Masuhara , Kenji Kaneko
发明人： Shojiro Asai , Toshiaki Masuhara , Kenji Kaneko
IPC分类号： H01L21/822 , H01L21/331 , H01L21/8222 , H01L27/04 , H01L27/06 , H01L27/082 , H01L27/088 , H01L29/73 , H01L29/78 , H03K19/082
CPC分类号： H01L27/088 , H01L27/082 , H01L29/7304
摘要： An electron device comprising (i) a semiconductor element which includes a semiconductor region A of a first conductivity type, a semiconductor region B of a second conductivity type adjoining the region A, and a semiconductor region C of the second conductivity type adjoining the region A and isolated from the region B by the region A, and in which on a surface extending from the region B via the region A to the region C, a gate electrode is provided through an insulating film, (ii) means for holding a potential of the gate electrode so that a potential of minority carriers in a surface portion of the region A underneath the gate electrode may become lower than a potential in an inner portion of the region A, (iii) means for applying a forward bias voltage between the region A and the region B, and (iv) means for applying to the region C a potential by which a potential for the minority carriers becomes lower in the region C than in the region B. The electron device is capable of such operations as amplification, oscillation and memory under an extraordinarily low supply voltage, and is extraordinarily low in the power consumption.
摘要翻译：一种电子器件，包括（i）半导体元件，其包括第一导电类型的半导体区域A，与区域A相邻的第二导电类型的半导体区域B和与区域A相邻的第二导电类型的半导体区域C 并且通过区域A从区域B隔离，并且其中在从区域B经由区域A延伸到区域C的表面上，通过绝缘膜提供栅电极，（ii）保持电位的装置使得栅极电极下面的区域A的表面部分中的少数载流子的电位可能变得低于区域A的内部部分中的电位，（iii）在区域A之间施加正向偏置电压的装置 A和区域B，以及（iv）用于向区域C施加在区域C中少于少数载流子的电位低于区域B的电位的装置。电子装置能够作为在非常低的电源电压下的放大，振荡和存储的操作，并且功耗非常低。

8. 发明授权

US4021835A Semiconductor device and a method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4021835A
公开(公告)日：1977-05-03
申请号：US544265
申请日：1975-01-27
申请人： Jun Etoh , Toshiaki Masuhara
发明人： Jun Etoh , Toshiaki Masuhara
IPC分类号： H01L21/265 , H01L29/78
CPC分类号： H01L29/7838 , H01L21/2652 , H01L29/78
摘要： A MOS-FET (Metal-Oxide-Semiconductor Field Effect Transistor) comprises a semiconductor body, source and drain regions disposed in the body at portions separated from each other, a second semiconductor region having a higher impurity concentration than that of the body, formed by ion implantation in the body between the source and drain regions, a first semiconductor region having a lower impurity concentration than that of the second semiconductor region but a higher impurity concentration than that of the body, and having an opposite conductivity type to that of the second semiconductor region, formed by ion implantation, so that the second semiconductor region is very thin, and which has a very small amount of a minute current, that is a tailing current.
摘要翻译： MOS-FET（金属氧化物半导体场效应晶体管）包括半导体本体，源极和漏极区域，其设置在彼此分离的部分的主体中，形成具有比主体杂质浓度更高的第二半导体区域通过在源极和漏极区域之间的体内离子注入，具有比第二半导体区域低的杂质浓度的杂质浓度较低的杂质浓度比第二半导体区域低的杂质浓度的第一半导体区域，并且具有与第二半导体区域，通过离子注入形成，使得第二半导体区域非常薄，并且具有非常少量的微小电流，即尾部电流。

9. 发明授权

US5332910A Semiconductor optical device with nanowhiskers 失效
标题翻译：具有纳米晶须的半导体光学器件
公开(公告)号：US5332910A
公开(公告)日：1994-07-26
申请号：US159343
申请日：1993-11-30
申请人： Keiichi Haraguchi , Kenji Hiruma , Kensuke Ogawa , Toshio Katsuyama , Ken Yamaguchi , Toshiyuki Usagawa , Masamits Yazawa , Toshiaki Masuhara , Gerard P. Morgan , Hiroshi Kakibayashi
发明人： Keiichi Haraguchi , Kenji Hiruma , Kensuke Ogawa , Toshio Katsuyama , Ken Yamaguchi , Toshiyuki Usagawa , Masamits Yazawa , Toshiaki Masuhara , Gerard P. Morgan , Hiroshi Kakibayashi
IPC分类号： G02B6/42 , H01L33/00 , H01L33/24 , H01S3/067 , H01S5/00 , H01S5/02 , H01S5/06 , H01S5/10 , H01S5/12 , H01S5/18 , H01S5/183 , H01S5/223 , H01S5/32 , H01S5/34 , H01S5/40 , H01S5/42 , H01S5/50
CPC分类号： H01L33/24 , B82Y20/00 , G02B6/4202 , H01L33/0062 , H01S5/1228 , H01S5/183 , H01S5/4031 , H01S3/06708 , H01S5/0028 , H01S5/0217 , H01S5/0608 , H01S5/1042 , H01S5/105 , H01S5/18 , H01S5/223 , H01S5/3202 , H01S5/3412 , H01S5/4006 , H01S5/4056 , H01S5/423 , H01S5/5045
摘要： A semiconductor light-emitting device includes a plurality of semiconductor rods, each of which has a pn junction. The semiconductor rods are formed on a semiconductor substrate such that the plurality of semiconductor rods are arranged at a distance substantially equal to an integer multiple of the wavelength of light emitted from the semiconductor rod. With such devices, various novel optical devices such as a micro-cavity laser of which the threshold current is extremely small and a coherent light-emitting device having no threshold value can be realized.
摘要翻译：半导体发光器件包括多个半导体棒，每个半导体棒具有pn结。半导体棒形成在半导体衬底上，使得多个半导体棒被布置成基本上等于从半导体棒发射的光的波长的整数倍的距离。利用这样的装置，可以实现各种新颖的光学装置，例如阈值电流极小的微腔激光器和不具有阈值的相干发光装置。

10. 发明授权

US4864382A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4864382A
公开(公告)日：1989-09-05
申请号：US148052
申请日：1988-01-25
申请人： Masaaki Aoki , Kazuo Yano , Toshiaki Masuhara
发明人： Masaaki Aoki , Kazuo Yano , Toshiaki Masuhara
IPC分类号： H01L27/108 , H01L29/10 , H01L29/167 , H01L29/66
CPC分类号： H01L29/66992 , H01L27/10805 , H01L29/1083 , H01L29/167 , Y10S257/919
摘要： A MOS memory is formed in a semiconductor bulk, whereas a barrier semiconductor layer is disposed at the boundary between a MOS memory portion and the semiconductor bulk in order to reduce the effect of undesirable carriers excited by .alpha.-particles. The barrier semiconductor layer is designed to permit operation of the memory at low temperature while reducing the incidence of soft errors due to .alpha.-particles.
摘要翻译：在半导体本体中形成MOS存储器，而在MOS存储器部分和半导体体之间的边界处设置阻挡半导体层，以便降低由α-粒子激发的不希望的载流子的影响。阻挡半导体层被设计为允许在低温下操作存储器，同时减少由于α-粒子引起的软错误的发生。

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