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1. 发明授权

US6066891A Electrode for semiconductor device including an alloy wiring layer for reducing defects in an aluminum layer and method for manufacturing the same 失效
标题翻译：包括用于减少铝层中的缺陷的合金布线层的半导体器件用电极及其制造方法
公开(公告)号：US6066891A
公开(公告)日：2000-05-23
申请号：US802214
申请日：1997-02-19
申请人： Tooru Yamaoka , Atsushi Komura , Takeshi Yamauchi , Yoshihiko Isobe , Hiroyuki Yamane
发明人： Tooru Yamaoka , Atsushi Komura , Takeshi Yamauchi , Yoshihiko Isobe , Hiroyuki Yamane
IPC分类号： H01L21/285 , H01L21/768 , H01L29/45 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76867 , H01L21/28518 , H01L21/76843 , H01L21/76846 , H01L21/76858 , H01L23/53223 , H01L29/456 , H01L2924/0002
摘要： The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 .mu.m, the number of Al voids with widths of over 0.3 .mu.m is practically reduced to 0.
摘要翻译：本发明的目的是为了获得能够抑制铝合金布线内的Al空隙的出现而不考虑这种铝合金布线的取向的半导体器件的电极布线结构。在硅衬底10的顶部上形成层间绝缘膜11，钛层12，用作阻挡层的氮化钛层13，铝合金布线层15和保护膜18，以构成电极结构。在这种情况下，在氮化钛层13和铝合金布线层15之间形成膜厚约为10nm以上的构成铝和钛的金属间化合物的失真弛豫层14 由于这种失真弛豫层，对于1μm的每个布线宽度，宽度大于0.3μm的Al空隙的数量实际上减少到0。

2. 发明授权

US06348735B1 Electrode for semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置用电极及其制造方法
公开(公告)号：US06348735B1
公开(公告)日：2002-02-19
申请号：US09482895
申请日：2000-01-14
申请人： Tooru Yamaoka , Atsushi Komura , Takeshi Yamauchi , Yoshihiko Isobe , Hiroyuki Yamane
发明人： Tooru Yamaoka , Atsushi Komura , Takeshi Yamauchi , Yoshihiko Isobe , Hiroyuki Yamane
IPC分类号： H01L2348
CPC分类号： H01L21/76867 , H01L21/28518 , H01L21/76843 , H01L21/76846 , H01L21/76858 , H01L23/53223 , H01L29/456 , H01L2924/0002 , H01L2924/00
摘要： The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 &mgr;m, the number of Al voids with widths of over 0.3 &mgr;m is practically reduced to 0.
摘要翻译：本发明的目的是为了获得能够抑制铝合金布线内的Al空隙的出现而不考虑这种铝合金布线的取向的半导体器件的电极布线结构。在硅衬底10的顶部上形成层间绝缘膜11，钛层12，用作阻挡层的氮化钛层13，铝合金布线层15和保护膜18，以构成电极结构。在这种情况下，在氮化钛层13和铝合金布线层15之间形成膜厚约为10nm以上的构成铝和钛的金属间化合物的失真弛豫层14 由于该失真弛豫层，对于1mum的每个布线宽度，宽度大于0.3μm的Al空隙的数量实际上减小到0。

3. 发明授权

US06908857B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06908857B2
公开(公告)日：2005-06-21
申请号：US10657081
申请日：2003-09-09
申请人： Kazuo Akamatsu , Yoshihiko Isobe , Hiroyuki Yamane
发明人： Kazuo Akamatsu , Yoshihiko Isobe , Hiroyuki Yamane
IPC分类号： H01L23/52 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/532 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/7685 , H01L21/28518 , H01L21/2855 , H01L21/32051 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate an Al alloy layer containing therein copper (Cu), and forming on the Al alloy layer a titanium nitride (TiN) film with enhanced chemical reactivity by using sputtering techniques while applying thereto a DC power of 5.5 W/cm2 or less. Fabrication of such reactivity-rich TiN film on the Al alloy layer results in a reaction layer of Al and Ti being subdivided into several spaced-apart segments. In this case, the reaction layer hardly serves as any diffusion path; thus, it becomes possible to prevent Cu as contained in the Al alloy layer from attempting to outdiffuse with the reaction layer being as its diffusion path. This makes it possible to suppress or minimize unwanted fabrication of AlN on or above the surface of an Al containing lead pattern, thereby enabling increase in electromigration (EM) lifetime of electrical interconnect leads used.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件具有硅衬底半导体元件和与其电连接的铝（Al）合金布线引线。该方法包括以下步骤：在硅衬底上形成含有铜（Cu）的Al合金层，并且通过使用溅射技术在Al合金层上形成具有增强的化学反应性的氮化钛（TiN）膜，同时施加直流电力为5.5W / cm 2以下。在Al合金层上制备这种富含反应性的TiN膜导致Al和Ti的反应层被细分成几个间隔开的段。在这种情况下，反应层几乎不作为任何扩散路径; 因此，可以防止Al合金层中所含的Cu作为其扩散路径而反向扩散。这使得可以抑制或最小化在含铝的引线图案的表面上或上方的AlN的不希望的制造，从而能够增加使用的电互连引线的电迁移（EM）寿命。

4. 发明授权

US06650017B1 Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime 有权
标题翻译：半导体器件的电气布线能够增加电迁移（EM）寿命
公开(公告)号：US06650017B1
公开(公告)日：2003-11-18
申请号：US09637066
申请日：2000-08-11
申请人： Kazuo Akamatsu , Yoshihiko Isobe , Hiroyuki Yamane
发明人： Kazuo Akamatsu , Yoshihiko Isobe , Hiroyuki Yamane
IPC分类号： H01L2348
CPC分类号： H01L21/7685 , H01L21/28518 , H01L21/2855 , H01L21/32051 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate an Al alloy layer containing therein copper (Cu), and forming on the Al alloy layer a titanium nitride (TiN) film with enhanced chemical reactivity by using sputtering techniques while applying thereto a DC power of 5.5 W/cm2 or less. Fabrication of such reactivity-rich TiN film on the Al alloy layer results in a reaction layer of Al and Ti being subdivided into several spaced-apart segments. In this case, the reaction layer hardly serves as any diffusion path; thus, it becomes possible to prevent Cu as contained in the Al alloy layer from attempting to outdiffuse with the reaction layer being as its diffusion path. This makes it possible to suppress or minimize unwanted fabrication of AlN on or above the surface of an Al containing lead pattern, thereby enabling increase in electromigration (EM) lifetime of electrical interconnect leads used.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件具有硅衬底半导体元件和与其电连接的铝（Al）合金布线引线。该方法包括以下步骤：在硅衬底上形成含有铜（Cu）的Al合金层，并且通过使用溅射技术在Al合金层上形成具有增强的化学反应性的氮化钛（TiN）膜，同时施加直流电力为5.5W / cm 2以下。在Al合金层上制备这种富含反应性的TiN膜导致Al和Ti的反应层被细分成几个间隔开的段。在这种情况下，反应层几乎不作为任何扩散路径; 因此，可以防止Al合金层中所含的Cu作为其扩散路径而反向扩散。这使得可以抑制或最小化在含铝的引线图案的表面上或上方的AlN的不希望的制造，从而能够增加使用的电互连引线的电迁移（EM）寿命。

5. 发明授权

US5675167A Enhancement-type semiconductor having reduced leakage current 失效
标题翻译：具有降低的漏电流的增强型半导体
公开(公告)号：US5675167A
公开(公告)日：1997-10-07
申请号：US562629
申请日：1995-11-24
申请人： Hiroyuki Yamane , Yasushi Higuchi , Mitsutaka Katada , Noriyuki Iwamori , Tsutomu Kawaguchi , Takeshi Kuzuhara
发明人： Hiroyuki Yamane , Yasushi Higuchi , Mitsutaka Katada , Noriyuki Iwamori , Tsutomu Kawaguchi , Takeshi Kuzuhara
IPC分类号： H01L21/336 , H01L27/088 , H01L27/112 , H01L29/10 , H01L29/76 , H01L27/01
CPC分类号： H01L29/66659 , H01L27/088 , H01L27/112 , H01L29/1045 , H01L29/1083
摘要： A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.
摘要翻译：公开了一种能够防止大的漏电流的具有增强型MOS结构的半导体器件。导致在增强型晶体管中形成在栅电极下方的沟道区域中的阈值调节用途的高浓度区域与源极区域连续并且不与漏极区域邻接。这里，设定高浓度区域和漏极区域之间的距离，以防止从漏极区域侧延伸的耗尽层到达高浓度区域。因此，耗尽层中的电场不会成为引起雪崩或齐纳击穿的关键场，因此可以减少漏电流。

6. 发明授权

US5036019A Method of producing a complementary-type semiconductor device 失效
标题翻译：互补型半导体器件的制造方法
公开(公告)号：US5036019A
公开(公告)日：1991-07-30
申请号：US537688
申请日：1990-06-13
申请人： Hiroyuki Yamane , Yasushi Higuchi
发明人： Hiroyuki Yamane , Yasushi Higuchi
IPC分类号： H01L29/78 , H01L21/266 , H01L21/336 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/266 , H01L21/823828 , H01L27/0928
摘要： A method of producing a MIS transistor such as a MOS transistor has a P type and an N type channel transistors. P type and N type well regions are provided with the N type and the P type channel transistors, respectively. Both the P type and the N type well regions are covered with an insulating film on which gate electrodes are formed in a predetermined pattern by means of a photo-resist. This photo-resist is used as a channelling block layer when an N type impurity is implanted into the P type well region near the gate electrode so as to form an N type diffusion layer. As a result, the photo-resist prevents the N type impurity from channelling into the gate electrode so that a leak current does not occur within the P type well region of the N type channel transistor.
摘要翻译： MOS晶体管等MIS晶体管的制造方法具有P型和N型沟道晶体管。 P型和N型阱区分别设置有N型和P型沟道晶体管。 P型和N型阱区均用绝缘膜覆盖，其上通过光刻胶以预定图案形成栅电极。当将N型杂质注入到栅极附近的P型阱区中时，该光刻胶用作沟道阻挡层，以形成N型扩散层。结果，光刻胶防止了N型杂质向栅电极的沟通，使得在N型沟道晶体管的P型阱区内不会发生漏电流。

7. 发明授权

US4250110A Method of preparing metoclopramide 失效
标题翻译：制备甲氧氯普胺的方法
公开(公告)号：US4250110A
公开(公告)日：1981-02-10
申请号：US58809
申请日：1979-07-19
申请人： Joji Nishikido , Nobuhiro Tamura , Yohei Fukuoka , Hiroyuki Yamane
发明人： Joji Nishikido , Nobuhiro Tamura , Yohei Fukuoka , Hiroyuki Yamane
IPC分类号： C07C231/00 , A61K31/165 , C07C67/00 , C07C231/02 , C07C231/12 , C07C235/50 , C07C235/60 , C07C237/44 , G07C20060101 , C07C103/82 , C07C101/42
CPC分类号： C07C235/50 , C07C231/02 , C07C231/12 , C07C235/46
摘要： 2-Chloro-4-N-(.beta.-diethylaminoethyl)aminocarbonyl-5-methoxy-benzamide of the formula, ##STR1## a process for their preparation and a process for preparing metoclopramide of the formula, ##STR2## using the above described 2-chloro-4-N-(.beta.-diethylaminoethyl)aminocarbonyl-5-methoxybenzamide.
摘要翻译：具有下式的2-氯-4-N-（β-二乙基氨基乙基）氨基羰基-5-甲氧基 - 苯甲酰胺，其制备方法和制备下式的甲氧氯普胺的方法，使用上述2 - 氯-4-N-（β-二乙基氨基乙基）氨基羰基-5-甲氧基苯甲酰胺。

8. 发明授权

US5216272A High withstanding voltage MIS transistor 失效
标题翻译：高耐压MIS晶体管
公开(公告)号：US5216272A
公开(公告)日：1993-06-01
申请号：US680148
申请日：1991-04-03
申请人： Ryoichi Kubokoya , Hiroyuki Yamane , Yasushi Higuchi
发明人： Ryoichi Kubokoya , Hiroyuki Yamane , Yasushi Higuchi
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/823814 , H01L27/0928 , H01L29/7835 , Y10S148/082
摘要： A high withstanding voltage MIS transistor, including an offset region and a double offset region in a region of a semiconductor substrate. The region of the semiconductor substrate has a first conductivity type. The offset region connects to a drain region, and has a second conductivity type. An impurity concentration of the offset region is lower than that of the drain region. The double offset region has the first conductivity type. At least a portion of the double offset region overlaps with the offset region. An impurity concentration of the double offset region is higher than that of the region of the semiconductor substrate. The disclosed structure has an improved current gain of the MIS transistor is improved.
摘要翻译：高耐压MIS晶体管，包括半导体衬底的区域中的偏移区域和双偏移区域。半导体衬底的区域具有第一导电类型。偏移区域连接到漏极区域，并且具有第二导电类型。偏移区域的杂质浓度低于漏极区域的杂质浓度。双偏移区具有第一导电类型。双偏移区域的至少一部分与偏移区域重叠。双偏移区域的杂质浓度高于半导体衬底区域的杂质浓度。所公开的结构具有改善的MIS晶体管的电流增益。

9. 发明授权

US5019526A Method of manufacturing a semiconductor device having a plurality of elements 失效
标题翻译：制造具有多个元件的半导体器件的方法
公开(公告)号：US5019526A
公开(公告)日：1991-05-28
申请号：US249514
申请日：1988-09-26
申请人： Hiroyuki Yamane , Yasushi Higuchi , Tetsuo Fujii
发明人： Hiroyuki Yamane , Yasushi Higuchi , Tetsuo Fujii
IPC分类号： H01L21/311 , H01L21/762
CPC分类号： H01L21/76213 , H01L21/31111 , H01L21/76216 , Y10S148/117 , Y10S438/911
摘要： A method of manufacturing a semiconductor apparatus having a plurality of elements formed on a substrate comprises forming a pad oxidized film on the surface of the semiconductor substrate, forming a pattern of silicon nitride film to coat device areas on the pad oxidized film, and injecting boron ions into that surface of the pad oxidized film where no silicon nitride film is present, thereby to form a channel stopper region. Using the pattern of the silicon nitride film as a mask, a heat oxidized film is then formed on an elements separating region by heat oxidization, and ions of Si, N, C, or the like are injected into the surface of the heat oxidized film with such an acceleration energy that the ions are not injected into the silicon nitride film thereby to change the quality of the heat oxidized film. The silicon nitride film is removed by etching and the heat oxidized film is etching-treated by a solution of the hydrofluoric acid group to etching-remove particularly the bird's beak portions each of which is present along and under the peripheral rim of an element area of the silicon nitride film.
摘要翻译：一种制造具有形成在基板上的多个元件的半导体装置的方法包括在半导体基板的表面上形成焊盘氧化膜，形成氮化硅膜的图案以涂覆焊盘氧化膜上的器件区域，并注入硼离子进入焊盘氧化膜的不存在氮化硅膜的表面，从而形成通道停止区域。使用氮化硅膜的图案作为掩模，然后通过热氧化在元件分离区域上形成热氧化膜，并且将Si，N，C等的离子注入到热氧化膜的表面具有这样的加速能量，使得离子不被注入到氮化硅膜中，从而改变热氧化膜的质量。通过蚀刻去除氮化硅膜，并且通过氢氟酸基团的溶液对热氧化膜进行蚀刻处理，特别是沿着元件区域的外围边缘沿着和/或氮化硅膜。

10. 发明授权

US4297503A Novel benzamide derivative and method of preparing metoclopramide using same 失效
标题翻译：新型苯甲酰胺衍生物和使用其制备甲氧氯普胺的方法
公开(公告)号：US4297503A
公开(公告)日：1981-10-27
申请号：US190994
申请日：1980-09-26
申请人： Joji Nishikido , Nobuhiro Tamura , Yohei Fukuoka , Hiroyuki Yamane
发明人： Joji Nishikido , Nobuhiro Tamura , Yohei Fukuoka , Hiroyuki Yamane
IPC分类号： C07C231/00 , A61K31/165 , C07C67/00 , C07C231/02 , C07C231/12 , C07C235/50 , C07C235/60 , C07C237/44 , G07C20060101 , C07C101/74
CPC分类号： C07C235/50 , C07C231/02 , C07C231/12 , C07C235/46
摘要： 2-Chloro-4-N-(.beta.-diethylaminoethyl)aminocarbonyl-5-methoxybenzamide of the formula, ##STR1## a process for their preparation and a process for preparing metoclopramide of the formula, ##STR2## using the above described 2-chloro-4-N-(.beta.-diethylaminoethyl)aminocarbonyl-5-methoxybenzamide.
摘要翻译：具有下式的2-氯-4-N-（β-二乙基氨基乙基）氨基羰基-5-甲氧基苯甲酰胺，其制备方法和制备下式的甲氧氯普胺的方法，使用上述2-氯 -4-N-（β-二乙基氨基乙基）氨基羰基-5-甲氧基苯甲酰胺。

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