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1. 发明申请

US20060234467A1 Method of forming trench isolation in a semiconductor device 审中-公开
标题翻译：在半导体器件中形成沟槽隔离的方法
公开(公告)号：US20060234467A1
公开(公告)日：2006-10-19
申请号：US11106822
申请日：2005-04-15
申请人： Toni Van Gompel , Glenn Abeln , Peter Beckage , Kyle Gilliland , Mohamad Jahanbani , James Burnett
发明人： Toni Van Gompel , Glenn Abeln , Peter Beckage , Kyle Gilliland , Mohamad Jahanbani , James Burnett
IPC分类号： H01L21/76
CPC分类号： G11C11/412 , H01L21/76237 , H01L27/11 , H01L27/1104
摘要： Divots (35, 36) may particularly be a problem for isolation trenches (22, 24) that are shallow. These divots (35, 36) may have a negative impact on the performance of the integrated circuit (49). Densification heating may be used to reduce the size and/or depth of these divots (35, 36) during manufacturing. For example, densification heating may be done at a temperature of at least 1100 degrees Celsius for at least 10 minutes after filling the isolation trenches (22, 24) with dielectric material (30). This densification heating may improve the variation in threshold voltages of transistors (e.g. 48) on an integrated circuit (49), particularly SOI (silicon on insulator) devices. SRAM cells (50) in particular may benefit from this densification heating.
摘要翻译：对于浅的隔离沟槽（22,24），特别是（35,36）可能是一个问题。这些故障（35,36）可能会对集成电路的性能产生负面影响（49）。在制造过程中，可以使用致密加热来减小这些纹理（35,36）的尺寸和/或深度。例如，在用介电材料（30）填充隔离沟槽（22,24）之后，可以在至少1100摄氏度的温度下进行致密化加热至少10分钟。这种致密化加热可以改善集成电路（49），特别是SOI（绝缘体上硅）器件上的晶体管（例如48）的阈值电压的变化。 SRAM单元（50）特别可以受益于该致密化加热。

2. 发明申请

US20070246793A1 Electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer and a process of forming the same 失效
标题翻译：包括半导体层和与半导体层内的开口相邻的另一层的电子器件及其形成工艺
公开(公告)号：US20070246793A1
公开(公告)日：2007-10-25
申请号：US11409633
申请日：2006-04-24
申请人： Toni Van Gompel , Peter Beckage , Mohamad Jahanbani , Michael Turner
发明人： Toni Van Gompel , Peter Beckage , Mohamad Jahanbani , Michael Turner
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/84 , H01L21/76283 , H01L21/823481 , H01L27/1203 , H01L29/78
摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening. The sidewall can extend from the surface towards the bottom of the opening. The process can also include forming a layer over the semiconductor layer and within the opening, and removing a part of the first layer from within the opening. After removing the part of the layer, a remaining portion of the layer may lie within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the layer may be spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the first layer.
摘要翻译：形成电子器件的工艺可以包括图案化半导体层以限定开口。在图案化半导体层之后，开口可以具有底部，并且半导体层可以具有侧壁和表面。表面与开口的底部间隔开。侧壁可以从开口的表面向底部延伸。该工艺还可以包括在半导体层之上和在开口内形成层，以及从开口内去除第一层的一部分。在去除层的一部分之后，层的剩余部分可以位于开口内并且邻近底部和侧壁，并且层的剩余部分可以与表面间隔开。在另一方面，电子设备可以包括包括第一层的场隔离区域。

3. 发明申请

US20050130359A1 Method and apparatus for elimination of excessive field oxide recess for thin Si SOI 有权
标题翻译：用于消除薄Si SOI的过量场氧化物凹陷的方法和装置
公开(公告)号：US20050130359A1
公开(公告)日：2005-06-16
申请号：US10737115
申请日：2003-12-16
申请人： Toni Van Gompel , Mark Hall , Mohamad Jahanbani , Michael Turner
发明人： Toni Van Gompel , Mark Hall , Mohamad Jahanbani , Michael Turner
IPC分类号： H01L21/762 , H01L21/336 , H01L21/8234
CPC分类号： H01L21/76283
摘要： A method for forming trench isolation in an SOI substrate begins with a pad oxide followed by an antireflective coating (ARC) over the upper semiconductor layer of the SOI substrate. The pad oxide is kept to a thickness not greater than about 100 Angstroms. An opening is formed for the trench isolation that extends into the oxide below the upper semiconductor layer to expose a surface thereof. The pad oxide is recessed along its sidewall with an isotropic etch. This is followed by a thin, not greater than 50 Angstroms, oxide grown along the sidewall of the opening. This grown oxide avoids forming a recess between the ARC and the pad oxide and also avoids forming a void between the surface of the lower oxide layer and the grown oxide. This results in avoiding polysilicon stringers when the subsequent polysilicon gate layer is formed.
摘要翻译：在SOI衬底中形成沟槽隔离的方法开始于衬底氧化物，然后在SOI衬底的上半导体层上方具有抗反射涂层（ARC）。衬垫氧化物保持不大于约100埃的厚度。形成用于沟槽隔离的开口，其延伸到上半导体层下方的氧化物中以暴露其表面。衬垫氧化物沿其侧壁凹陷，具有各向同性蚀刻。其后是沿着开口的侧壁生长的薄的，不大于50埃的氧化物。这种生长的氧化物避免在ARC和衬垫氧化物之间形成凹陷，并且还避免在低氧化物层的表面和生长的氧化物之间形成空隙。这导致当形成随后的多晶硅栅极层时避免多晶硅桁条。

4. 发明申请

US20070249160A1 Process of forming an electronic device including a layer formed using an inductively coupled plasma 有权
标题翻译：形成电子器件的工艺包括使用电感耦合等离子体形成的层
公开(公告)号：US20070249160A1
公开(公告)日：2007-10-25
申请号：US11409790
申请日：2006-04-24
申请人： Michael Turner , Mohamad Jahanbani , Toni Van Gompel , Mark Hall
发明人： Michael Turner , Mohamad Jahanbani , Toni Van Gompel , Mark Hall
IPC分类号： H01L21/4763
CPC分类号： H01L21/02274 , H01L21/02211 , H01L21/02236 , H01L21/02255 , H01L21/3185 , H01L21/76283 , H01L21/823481 , H01L21/84
摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning a semiconductor layer, the semiconductor layer can have a sidewall and a surface, the surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include chemical vapor depositing a first layer adjacent to the sidewall, wherein the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. Chemical vapor depositing the first layer can be performed using an inductively coupled plasma.
摘要翻译：形成电子器件的过程可以包括图案化半导体层以限定延伸到绝缘层的开口，其中绝缘层位于衬底和半导体层之间。在图案化半导体层之后，半导体层可以具有侧壁和表面，表面可以与绝缘层间隔开，并且侧壁可以从表面延伸到绝缘层。该方法还可以包括化学气相沉积邻近侧壁的第一层，其中第一层位于开口内且与侧壁相邻并且与表面间隔开。可以使用电感耦合等离子体进行沉积第一层的化学气相沉积。

5. 发明申请

US20060223266A1 Method of forming an electronic device 有权
标题翻译：电子设备的形成方法
公开(公告)号：US20060223266A1
公开(公告)日：2006-10-05
申请号：US11098874
申请日：2005-04-05
申请人： Sangwoo Lim , Paul Grudowski , Mohamad Jahanbani , Hsing Tseng , Choh-Fei Yeap
发明人： Sangwoo Lim , Paul Grudowski , Mohamad Jahanbani , Hsing Tseng , Choh-Fei Yeap
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462
摘要： A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.
摘要翻译：一种形成电子器件的方法包括蚀刻第一栅极电介质层的一部分以减小该部分内的栅极电介质层的厚度。在一个实施例中，未被蚀刻的部分可以被掩模覆盖。在另一个实施例中，不同部分可以在不同时间被蚀刻，以给予第一栅极介电层不同的厚度。在特定实施例中，可以在蚀刻该部分之后在第一栅极电介质层上形成第二栅极电介质层。第二栅极介电层可以具有大于第一栅极介电层的介电常数的介电常数。可以进行随后的栅电极和源/漏区形成以形成晶体管结构。

6. 发明申请

US20070295357A1 REMOVING METAL USING AN OXIDIZING CHEMISTRY 审中-公开
标题翻译：使用氧化化学除去金属
公开(公告)号：US20070295357A1
公开(公告)日：2007-12-27
申请号：US11426755
申请日：2006-06-27
申请人： Michael Lovejoy , Ross Noble , Mohamad Jahanbani
发明人： Michael Lovejoy , Ross Noble , Mohamad Jahanbani
IPC分类号： C23G1/00 , H01L21/306
CPC分类号： H01L21/32134 , C23F1/30 , H01L21/02068 , H01L21/28052 , H01L21/28114 , H01L21/6708 , H01L21/67086 , H01L29/665 , H01L29/66628
摘要： A method of removing a metal includes exposing at least a portion of a metal-to-metal removal chemistry, wherein the metal removal chemistry comprises a chlorine-rich superoxidizer. In one embodiment, the metal being removed is a metal, such as a noble metal, that did not react with the semiconductor device during a salicidation process. In one embodiment, the chlorine-rich superoxidizer is formed by mixing hydrochloric acid in gas form with hydrogen peroxide and sulfuric acid. The metal can be exposed to the chlorine-rich superoxidizer in various ways, such as through an immersion or spray process.
摘要翻译：除去金属的方法包括暴露金属对金属去除化学物质的至少一部分，其中金属去除化学物质包含富含氯的超氧化剂。在一个实施例中，被去除的金属是在盐析过程中不与半导体器件反应的金属，例如贵金属。在一个实施方案中，通过将气体形式的盐酸与过氧化氢和硫酸混合而形成富氯超氧化剂。金属可以以各种方式例如通过浸渍或喷涂方法暴露于富含氯的超氧化剂中。

7. 发明申请

US20060115949A1 Semiconductor fabrication process including source/drain recessing and filling 审中-公开
标题翻译：半导体制造工艺包括源极/漏极凹陷和填充
公开(公告)号：US20060115949A1
公开(公告)日：2006-06-01
申请号：US11000717
申请日：2004-12-01
申请人： Da Zhang , Mohamad Jahanbani , Bich-Yen Nguyen , Ross Noble
发明人： Da Zhang , Mohamad Jahanbani , Bich-Yen Nguyen , Ross Noble
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L29/7834 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor fabrication process includes forming a gate dielectric overlying a silicon substrate and forming a gate electrode overlying the gate dielectric. Source/drain recesses are then formed in the substrate on either side of the gate electrode using an NH4OH-based wet etch. A silicon-bearing semiconductor compound is then formed epitaxially to fill the source/drain recesses and thereby create source/drain structures. Exposed dielectric on the substrate upper surface may be removed using an HF dip prior to forming the source/drain recesses. Preferably, the NH4OH solution has an NH4OH concentration of less than approximately 0.5% and is maintained a temperature in the range of approximately 20 to 35° C. The silicon-bearing epitaxial compound may be silicon germanium for PMOS transistor or silicon carbide for NMOS transistors. A silicon dry etch process may be performed prior to the NH4OH wet etch to remove a surface portion of the source/drain regions.
摘要翻译：半导体制造工艺包括形成覆盖硅衬底的栅极电介质并形成覆盖栅极电介质的栅电极。然后使用基于NH 4 OH的湿蚀刻在栅电极的任一侧上的衬底中形成源极/漏极凹陷。然后外延形成含硅半导体化合物以填充源极/漏极凹部，从而产生源极/漏极结构。在形成源极/漏极凹部之前，可以使用HF浸渍来去除衬底上表面上的暴露电介质。优选地，NH 4 OH溶液具有小于约0.5％的NH 4 OH浓度，并且保持在约20至35℃范围内的温度。含硅外延化合物可以是用于PMOS晶体管的硅锗或用于NMOS晶体管的碳化硅。硅干蚀刻工艺可以在NH 4 OH湿法蚀刻之前进行，以除去源/漏区的表面部分。

8. 发明授权

US07037857B2 Method for elimination of excessive field oxide recess for thin Si SOI 有权
标题翻译：消除薄Si SOI的过量场氧化物凹陷的方法
公开(公告)号：US07037857B2
公开(公告)日：2006-05-02
申请号：US10737115
申请日：2003-12-16
申请人： Toni D. Van Gompel , Mark D. Hall , Mohamad Jahanbani , Michael D. Turner
发明人： Toni D. Van Gompel , Mark D. Hall , Mohamad Jahanbani , Michael D. Turner
IPC分类号： H01L21/3205 , H01L21/31
CPC分类号： H01L21/76283
摘要： A method for forming trench isolation in an SOI substrate begins with a pad oxide followed by an antireflective coating (ARC) over the upper semiconductor layer of the SOI substrate. The pad oxide is kept to a thickness not greater than about 100 Angstroms. An opening is formed for the trench isolation that extends into the oxide below the upper semiconductor layer to expose a surface thereof. The pad oxide is recessed along its sidewall with an isotropic etch. This is followed by a thin, not greater than 50 Angstroms, oxide grown along the sidewall of the opening. This grown oxide avoids forming a recess between the ARC and the pad oxide and also avoids forming a void between the surface of the lower oxide layer and the grown oxide. This results in avoiding polysilicon stringers when the subsequent polysilicon gate layer is formed.
摘要翻译：在SOI衬底中形成沟槽隔离的方法开始于衬底氧化物，然后在SOI衬底的上半导体层上方具有抗反射涂层（ARC）。衬垫氧化物保持不大于约100埃的厚度。形成用于沟槽隔离的开口，其延伸到上半导体层下方的氧化物中以暴露其表面。衬垫氧化物沿其侧壁凹陷，具有各向同性蚀刻。其后是沿着开口的侧壁生长的薄的，不大于50埃的氧化物。这种生长的氧化物避免在ARC和衬垫氧化物之间形成凹陷，并且还避免在低氧化物层的表面和生长的氧化物之间形成空隙。这导致当形成随后的多晶硅栅极层时避免多晶硅桁条。

9. 发明授权

US06564469B2 Device for performing surface treatment on semiconductor wafers 失效
标题翻译：用于在半导体晶片上进行表面处理的装置
公开(公告)号：US06564469B2
公开(公告)日：2003-05-20
申请号：US09901381
申请日：2001-07-09
申请人： Mohamad Jahanbani , Stefan Ruemmelin , Ronald Hoyer
发明人： Mohamad Jahanbani , Stefan Ruemmelin , Ronald Hoyer
IPC分类号： F26B2106
CPC分类号： H01L21/67051 , H01L21/67057 , H01L21/67386
摘要： A device for performing surface treatment on semiconductor wafers has a cassette (1) for accommodating a plurality of wafers (5) in its interior (3); the wafers (5) are aligned in a first row. The wafer surfaces (51) are essentially in parallel with each other. The cassette (1) has a side-wall (10) which can be arranged essentially perpendicular with respect to the wafer surfaces (51); the side-wall (10) has openings (111′-145′) on its face (101) which is directed to the wafers (5), the openings (111′-145′) are aligned in second rows, the second rows are essentially parallel to the first row; the openings (111′-114′) are connected to respective supply channels (11′, 12′, 13′, 14′, 15′) for transporting a surface treatment medium which is fed to one (15′) of these supply channels via a feeding point (FP). The cross-section of the openings (111′-145′) is variable.
摘要翻译：用于在半导体晶片上进行表面处理的装置具有用于在其内部（3）容纳多个晶片（5）的盒（1）。晶片（5）在第一排中排列。晶片表面（51）基本上彼此平行。盒（1）具有可相对于晶片表面（51）基本垂直布置的侧壁（10）。所述侧壁（10）在其面（101）上具有指向晶片（5）的开口（111'-145'），所述开口（111'-145'）在第二排中排列，所述第二排基本上平行于第一排; 开口（111'-114'）连接到相应的供应通道（11'，12'，13'，14'，15'），用于输送供给到这些供应通道中的一个（15'）的表面处理介质通过馈电点（FP）。开口（111'-145'）的横截面是可变的。

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