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1. 发明申请

US20070264839A1 Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer 有权
标题翻译：形成电子器件的工艺包括与半导体层内的开口相邻的致密的氮化物层
公开(公告)号：US20070264839A1
公开(公告)日：2007-11-15
申请号：US11433298
申请日：2006-05-12
申请人： Toni Van Gompel , Kuang-hsin Chen , Laegu Kang , Rode Mora , Michael Turner
发明人： Toni Van Gompel , Kuang-hsin Chen , Laegu Kang , Rode Mora , Michael Turner
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31111 , H01L21/3105 , H01L21/31116 , H01L21/76205
摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique. The process can further include densifying the nitride layer. The process can still further include removing a part of the nitride layer, wherein a remaining portion of the nitride layer can lie within the opening and be spaced apart from the surface.
摘要翻译：形成电子器件的过程可以包括图案化半导体层以限定延伸到绝缘层的开口，其中绝缘层位于衬底和半导体层之间。在图案化半导体层之后，开口可以具有底部，并且半导体层可以具有侧壁和表面。表面可以与绝缘层间隔开，并且侧壁可以从表面延伸到绝缘层。该方法还可以包括在开口内沉积氮化物层，其中使用PECVD技术进行沉积。该方法还可以包括使氮化物层致密化。该方法还可以进一步包括去除氮化物层的一部分，其中氮化物层的剩余部分可以位于开口内并且与表面间隔开。

2. 发明申请

US20070224772A1 Method for forming a stressor structure 审中-公开
标题翻译：形成应力结构的方法
公开(公告)号：US20070224772A1
公开(公告)日：2007-09-27
申请号：US11386539
申请日：2006-03-21
申请人： Mark Hall , Rode Mora , Michael Turner , Laegu Kang , Toni Van Gompel , Stanley Filipiak
发明人： Mark Hall , Rode Mora , Michael Turner , Laegu Kang , Toni Van Gompel , Stanley Filipiak
IPC分类号： H01L21/76
CPC分类号： H01L21/76283 , H01L21/76286 , H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises an active semiconductor layer (224) disposed on a buried dielectric layer (222). A trench (229) is created in the semiconductor structure which exposes a portion of the buried dielectric layer. An oxide layer (250) is formed over the surfaces of the trench, and at least one stressor structure (255) is formed over the oxide layer.
摘要翻译：本发明提供制造半导体器件的方法。根据该方法，提供了一种半导体结构，其包括设置在掩埋介电层（222）上的有源半导体层（224）。在半导体结构中形成沟槽（229），其暴露了一部分埋入的介质层。在沟槽的表面上形成氧化物层（250），在氧化物层上形成至少一个应力源结构（255）。

3. 发明申请

US20070249129A1 STI stressor integration for minimal phosphoric exposure and divot-free topography 审中-公开
标题翻译： STI压力整合为最小的磷酸暴露和无地形的地形
公开(公告)号：US20070249129A1
公开(公告)日：2007-10-25
申请号：US11408346
申请日：2006-04-21
申请人： Mark Hall , Peter Beckage , John Hackenberg , Toni Van Gompel
发明人： Mark Hall , Peter Beckage , John Hackenberg , Toni Van Gompel
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises an active semiconductor layer (224) disposed on a buried dielectric layer (222). A trench (229) is created in the semiconductor structure which exposes a portion of the buried dielectric layer. An oxide layer (250) is formed over the surfaces of the trench, and at least one stressor structure (254) is formed over the oxide layer.
摘要翻译：本发明提供制造半导体器件的方法。根据该方法，提供了一种半导体结构，其包括设置在掩埋介电层（222）上的有源半导体层（224）。在半导体结构中形成沟槽（229），其暴露了一部分埋入的介质层。在沟槽的表面上形成氧化物层（250），在氧化物层上形成至少一个应力源结构（254）。

4. 发明申请

US20070249127A1 Electronic device including a semiconductor layer and a sidewall spacer and a process of forming the same 审中-公开
标题翻译：包括半导体层和侧壁间隔物的电子器件及其制造方法
公开(公告)号：US20070249127A1
公开(公告)日：2007-10-25
申请号：US11409882
申请日：2006-04-24
申请人： Rode Mora , Vance Adams , Venkat Kolagunta , Michael Turner , Toni Van Gompel
发明人： Rode Mora , Vance Adams , Venkat Kolagunta , Michael Turner , Toni Van Gompel
IPC分类号： H01L21/336 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203
摘要： An electronic device can include a substrate, an insulating layer, and a semiconductor layer overlying the insulating layer, wherein the insulating layer lies between the substrate and the semiconductor layer. In one aspect, a process of forming the electronic device can include patterning the semiconductor layer to define an opening extending to the insulating layer. The semiconductor layer has a sidewall and a surface, the surface is spaced apart from the insulating layer, and the sidewall extends from the surface towards the insulating layer. The process can also include forming a sidewall spacer adjacent to the sidewall, wherein the sidewall spacer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the sidewall spacer.
摘要翻译：电子器件可以包括衬底，绝缘层和覆盖绝缘层的半导体层，其中绝缘层位于衬底和半导体层之间。一方面，形成电子器件的工艺可以包括图案化半导体层以限定延伸到绝缘层的开口。半导体层具有侧壁和表面，表面与绝缘层间隔开，并且侧壁从表面向绝缘层延伸。该方法还可以包括形成邻近侧壁的侧壁间隔物，其中侧壁间隔物位于开口内且与侧壁相邻并且与表面间隔开。在另一方面，电子设备可以包括包括侧壁间隔物的场隔离区域。

5. 发明申请

US20070246793A1 Electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer and a process of forming the same 失效
标题翻译：包括半导体层和与半导体层内的开口相邻的另一层的电子器件及其形成工艺
公开(公告)号：US20070246793A1
公开(公告)日：2007-10-25
申请号：US11409633
申请日：2006-04-24
申请人： Toni Van Gompel , Peter Beckage , Mohamad Jahanbani , Michael Turner
发明人： Toni Van Gompel , Peter Beckage , Mohamad Jahanbani , Michael Turner
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/84 , H01L21/76283 , H01L21/823481 , H01L27/1203 , H01L29/78
摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening. The sidewall can extend from the surface towards the bottom of the opening. The process can also include forming a layer over the semiconductor layer and within the opening, and removing a part of the first layer from within the opening. After removing the part of the layer, a remaining portion of the layer may lie within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the layer may be spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the first layer.
摘要翻译：形成电子器件的工艺可以包括图案化半导体层以限定开口。在图案化半导体层之后，开口可以具有底部，并且半导体层可以具有侧壁和表面。表面与开口的底部间隔开。侧壁可以从开口的表面向底部延伸。该工艺还可以包括在半导体层之上和在开口内形成层，以及从开口内去除第一层的一部分。在去除层的一部分之后，层的剩余部分可以位于开口内并且邻近底部和侧壁，并且层的剩余部分可以与表面间隔开。在另一方面，电子设备可以包括包括第一层的场隔离区域。

6. 发明申请

US20060261436A1 Electronic device including a trench field isolation region and a process for forming the same 审中-公开
标题翻译：包括沟槽场隔离区域的电子器件及其形成方法
公开(公告)号：US20060261436A1
公开(公告)日：2006-11-23
申请号：US11132936
申请日：2005-05-19
申请人： Michael Turner , John Hackenberg , Toni Van Gompel
发明人： Michael Turner , John Hackenberg , Toni Van Gompel
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L29/78 , H01L21/76283 , H01L21/84
摘要： A process can be used to achieve the benefits of corner rounding of a semiconductor layer near an edge of a trench field isolation region without having the bird's beak or stress issues that occur with a conventional SOI device. A trench can be partially etched into a semiconductor layer, and a liner layer may be formed to help round corners of the second semiconductor layer. In one embodiment, the trench can be etched deeper and potentially expose an underlying buried oxide layer. Formation of the trench field isolation region can be completed, and electronic components can be formed within the semiconductor layer. An electronic device, such as an integrated circuit, will have a liner layer that extends only partly, but not completely, along a sidewall of the trench. In another embodiment, the process can be extended to other substrates and is not limited only to SOI substrates.
摘要翻译：可以使用一种方法来实现在沟槽场隔离区域的边缘附近的半导体层的圆角化的优点，而不会发生与常规SOI器件发生的鸟嘴或应力问题。可以将沟槽部分地蚀刻到半导体层中，并且可以形成衬垫层以帮助第二半导体层的圆角。在一个实施例中，可以更深地蚀刻沟槽并且潜在地暴露下面的掩埋氧化物层。可以完成沟槽场隔离区的形成，并且可以在半导体层内形成电子部件。诸如集成电路的电子装置将具有仅沿着沟槽的侧壁部分但不完全延伸的衬垫层。在另一个实施例中，该工艺可以扩展到其它衬底，并且不仅限于SOI衬底。

7. 发明申请

US20050130359A1 Method and apparatus for elimination of excessive field oxide recess for thin Si SOI 有权
标题翻译：用于消除薄Si SOI的过量场氧化物凹陷的方法和装置
公开(公告)号：US20050130359A1
公开(公告)日：2005-06-16
申请号：US10737115
申请日：2003-12-16
申请人： Toni Van Gompel , Mark Hall , Mohamad Jahanbani , Michael Turner
发明人： Toni Van Gompel , Mark Hall , Mohamad Jahanbani , Michael Turner
IPC分类号： H01L21/762 , H01L21/336 , H01L21/8234
CPC分类号： H01L21/76283
摘要： A method for forming trench isolation in an SOI substrate begins with a pad oxide followed by an antireflective coating (ARC) over the upper semiconductor layer of the SOI substrate. The pad oxide is kept to a thickness not greater than about 100 Angstroms. An opening is formed for the trench isolation that extends into the oxide below the upper semiconductor layer to expose a surface thereof. The pad oxide is recessed along its sidewall with an isotropic etch. This is followed by a thin, not greater than 50 Angstroms, oxide grown along the sidewall of the opening. This grown oxide avoids forming a recess between the ARC and the pad oxide and also avoids forming a void between the surface of the lower oxide layer and the grown oxide. This results in avoiding polysilicon stringers when the subsequent polysilicon gate layer is formed.
摘要翻译：在SOI衬底中形成沟槽隔离的方法开始于衬底氧化物，然后在SOI衬底的上半导体层上方具有抗反射涂层（ARC）。衬垫氧化物保持不大于约100埃的厚度。形成用于沟槽隔离的开口，其延伸到上半导体层下方的氧化物中以暴露其表面。衬垫氧化物沿其侧壁凹陷，具有各向同性蚀刻。其后是沿着开口的侧壁生长的薄的，不大于50埃的氧化物。这种生长的氧化物避免在ARC和衬垫氧化物之间形成凹陷，并且还避免在低氧化物层的表面和生长的氧化物之间形成空隙。这导致当形成随后的多晶硅栅极层时避免多晶硅桁条。

8. 发明申请

US20060234467A1 Method of forming trench isolation in a semiconductor device 审中-公开
标题翻译：在半导体器件中形成沟槽隔离的方法
公开(公告)号：US20060234467A1
公开(公告)日：2006-10-19
申请号：US11106822
申请日：2005-04-15
申请人： Toni Van Gompel , Glenn Abeln , Peter Beckage , Kyle Gilliland , Mohamad Jahanbani , James Burnett
发明人： Toni Van Gompel , Glenn Abeln , Peter Beckage , Kyle Gilliland , Mohamad Jahanbani , James Burnett
IPC分类号： H01L21/76
CPC分类号： G11C11/412 , H01L21/76237 , H01L27/11 , H01L27/1104
摘要： Divots (35, 36) may particularly be a problem for isolation trenches (22, 24) that are shallow. These divots (35, 36) may have a negative impact on the performance of the integrated circuit (49). Densification heating may be used to reduce the size and/or depth of these divots (35, 36) during manufacturing. For example, densification heating may be done at a temperature of at least 1100 degrees Celsius for at least 10 minutes after filling the isolation trenches (22, 24) with dielectric material (30). This densification heating may improve the variation in threshold voltages of transistors (e.g. 48) on an integrated circuit (49), particularly SOI (silicon on insulator) devices. SRAM cells (50) in particular may benefit from this densification heating.
摘要翻译：对于浅的隔离沟槽（22,24），特别是（35,36）可能是一个问题。这些故障（35,36）可能会对集成电路的性能产生负面影响（49）。在制造过程中，可以使用致密加热来减小这些纹理（35,36）的尺寸和/或深度。例如，在用介电材料（30）填充隔离沟槽（22,24）之后，可以在至少1100摄氏度的温度下进行致密化加热至少10分钟。这种致密化加热可以改善集成电路（49），特别是SOI（绝缘体上硅）器件上的晶体管（例如48）的阈值电压的变化。 SRAM单元（50）特别可以受益于该致密化加热。

9. 发明申请

US20070249160A1 Process of forming an electronic device including a layer formed using an inductively coupled plasma 有权
标题翻译：形成电子器件的工艺包括使用电感耦合等离子体形成的层
公开(公告)号：US20070249160A1
公开(公告)日：2007-10-25
申请号：US11409790
申请日：2006-04-24
申请人： Michael Turner , Mohamad Jahanbani , Toni Van Gompel , Mark Hall
发明人： Michael Turner , Mohamad Jahanbani , Toni Van Gompel , Mark Hall
IPC分类号： H01L21/4763
CPC分类号： H01L21/02274 , H01L21/02211 , H01L21/02236 , H01L21/02255 , H01L21/3185 , H01L21/76283 , H01L21/823481 , H01L21/84
摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning a semiconductor layer, the semiconductor layer can have a sidewall and a surface, the surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include chemical vapor depositing a first layer adjacent to the sidewall, wherein the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. Chemical vapor depositing the first layer can be performed using an inductively coupled plasma.
摘要翻译：形成电子器件的过程可以包括图案化半导体层以限定延伸到绝缘层的开口，其中绝缘层位于衬底和半导体层之间。在图案化半导体层之后，半导体层可以具有侧壁和表面，表面可以与绝缘层间隔开，并且侧壁可以从表面延伸到绝缘层。该方法还可以包括化学气相沉积邻近侧壁的第一层，其中第一层位于开口内且与侧壁相邻并且与表面间隔开。可以使用电感耦合等离子体进行沉积第一层的化学气相沉积。

10. 发明申请

US20050242403A1 Isolation trench 有权
公开(公告)号：US20050242403A1
公开(公告)日：2005-11-03
申请号：US10836150
申请日：2004-04-30
申请人： Choh-Fei Yeap , Yongjoo Jeon , Michael Turner , Toni Van Gompel
发明人： Choh-Fei Yeap , Yongjoo Jeon , Michael Turner , Toni Van Gompel
IPC分类号： H01L21/302 , H01L21/461 , H01L21/76 , H01L21/762 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76283 , H01L21/84
摘要： A process for forming an isolation trench in a wafer. The process includes depositing (e.g. by a directional deposition process) a first dielectric material in the trench and then depositing a second dielectric material (e.g. by a directional deposition process) over the first dielectric material in the trench. A third material is deposited in the trench on the second layer. The second material and the third material are selectively etchable with respect to each other. In one example, the first material has a lower dielectric constant than the second material.

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