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1. 发明申请

US20060115949A1 Semiconductor fabrication process including source/drain recessing and filling 审中-公开
标题翻译：半导体制造工艺包括源极/漏极凹陷和填充
公开(公告)号：US20060115949A1
公开(公告)日：2006-06-01
申请号：US11000717
申请日：2004-12-01
申请人： Da Zhang , Mohamad Jahanbani , Bich-Yen Nguyen , Ross Noble
发明人： Da Zhang , Mohamad Jahanbani , Bich-Yen Nguyen , Ross Noble
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L29/7834 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor fabrication process includes forming a gate dielectric overlying a silicon substrate and forming a gate electrode overlying the gate dielectric. Source/drain recesses are then formed in the substrate on either side of the gate electrode using an NH4OH-based wet etch. A silicon-bearing semiconductor compound is then formed epitaxially to fill the source/drain recesses and thereby create source/drain structures. Exposed dielectric on the substrate upper surface may be removed using an HF dip prior to forming the source/drain recesses. Preferably, the NH4OH solution has an NH4OH concentration of less than approximately 0.5% and is maintained a temperature in the range of approximately 20 to 35° C. The silicon-bearing epitaxial compound may be silicon germanium for PMOS transistor or silicon carbide for NMOS transistors. A silicon dry etch process may be performed prior to the NH4OH wet etch to remove a surface portion of the source/drain regions.
摘要翻译：半导体制造工艺包括形成覆盖硅衬底的栅极电介质并形成覆盖栅极电介质的栅电极。然后使用基于NH 4 OH的湿蚀刻在栅电极的任一侧上的衬底中形成源极/漏极凹陷。然后外延形成含硅半导体化合物以填充源极/漏极凹部，从而产生源极/漏极结构。在形成源极/漏极凹部之前，可以使用HF浸渍来去除衬底上表面上的暴露电介质。优选地，NH 4 OH溶液具有小于约0.5％的NH 4 OH浓度，并且保持在约20至35℃范围内的温度。含硅外延化合物可以是用于PMOS晶体管的硅锗或用于NMOS晶体管的碳化硅。硅干蚀刻工艺可以在NH 4 OH湿法蚀刻之前进行，以除去源/漏区的表面部分。

2. 发明授权

US07800141B2 Electronic device including a semiconductor fin 有权
标题翻译：包括半导体鳍片的电子设备
公开(公告)号：US07800141B2
公开(公告)日：2010-09-21
申请号：US12174357
申请日：2008-07-16
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66507 , H01L29/66795 , H01L29/78684
摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
摘要翻译：电子器件可以包括覆盖绝缘层的半导体鳍片。电子器件还可以包括覆盖半导体鳍片的半导体层。半导体层可以具有彼此间隔开的第一部分和第二部分。在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。电子器件还可以包括覆盖半导体层的金属 - 半导体层。在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

3. 发明授权

US07446026B2 Method of forming a CMOS device with stressor source/drain regions 有权
标题翻译：形成具有应力源/漏极区域的CMOS器件的方法
公开(公告)号：US07446026B2
公开(公告)日：2008-11-04
申请号：US11349595
申请日：2006-02-08
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/823814 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion over the dielectric, a first in situ doped semiconductor portion over the metal portion, and a first blocking cap over the in situ doped semiconductor portion. The method further includes performing implantations to form source/drain regions adjacent the first and second gate stack, where the first blocking cap has a thickness sufficient to substantially block implant dopants from entering the first in situ doped semiconductor portion. Source/drain embedded stressors are also formed.
摘要翻译：一种用于形成半导体器件的方法包括提供具有第一掺杂区域和第二掺杂区域的半导体衬底，在第一掺杂区域和第二掺杂区域上提供电介质，以及在电介质上至少形成第一栅极叠层第一掺杂区域的一部分。第一栅极堆叠包括电介质上的金属部分，金属部分上方的第一原位掺杂半导体部分以及原位掺杂半导体部分上的第一阻挡盖。该方法还包括执行注入以形成与第一和第二栅极堆叠相邻的源极/漏极区域，其中第一阻挡盖具有足以基本上阻挡注入掺杂剂进入第一原位掺杂半导体部分的厚度。源/漏嵌入式应力源也形成。

4. 发明授权

US07413970B2 Process of forming an electronic device including a semiconductor fin 有权
标题翻译：形成包括半导体鳍片的电子器件的工艺
公开(公告)号：US07413970B2
公开(公告)日：2008-08-19
申请号：US11375894
申请日：2006-03-15
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L29/06 , H01L21/3205
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66507 , H01L29/66795 , H01L29/78684
摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
摘要翻译：电子器件可以包括覆盖绝缘层的半导体鳍片。电子器件还可以包括覆盖半导体鳍片的半导体层。半导体层可以具有彼此间隔开的第一部分和第二部分。在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。电子器件还可以包括覆盖半导体层的金属 - 半导体层。在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

5. 发明申请

US20080014688A1 SELECTIVE UNIAXIAL STRESS MODIFICATION FOR USE WITH STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT 有权
标题翻译：绝缘子集成电路上使用应变硅的选择性单相应力变形
公开(公告)号：US20080014688A1
公开(公告)日：2008-01-17
申请号：US11428953
申请日：2006-07-06
申请人： Voon-Yew Thean , Bich-Yen Nguyen , Da Zhang
发明人： Voon-Yew Thean , Bich-Yen Nguyen , Da Zhang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., H2 or GeH2, maintained at a temperature in the range of approximately 800 to 1000° C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.
摘要翻译：半导体制造工艺包括掩蔽半导体晶片的第一区域（例如，NMOS区域），例如双轴拉伸应变绝缘体上硅（SOI）晶片，并在第二晶片区域的源/漏区域中产生凹陷，例如，PMOS区域。然后将晶片在促进硅迁移的环境中退火。源极/漏极凹槽用源极/漏极结构填充，例如通过外延生长。退火环境可以包括保持在约800至1000℃范围内的温度的含氢物质，例如H 2 H 2或GeH 2 H 2。第二区域可以是硅，并且源极/漏极结构可以是硅锗。创建凹槽可以包括用第一蚀刻工艺创建浅凹槽，执行非晶化注入以产生非晶层，执行惰性环境退火以使非晶层重结晶，以及用第二蚀刻工艺加深浅凹槽。

6. 发明授权

US07282415B2 Method for making a semiconductor device with strain enhancement 有权
标题翻译：制造具有应变增强的半导体器件的方法
公开(公告)号：US07282415B2
公开(公告)日：2007-10-16
申请号：US11092291
申请日：2005-03-29
申请人： Da Zhang , Bich-Yen Nguyen , Voon-Yew Thean , Yasuhito Shiho , Veer Dhandapani
发明人： Da Zhang , Bich-Yen Nguyen , Voon-Yew Thean , Yasuhito Shiho , Veer Dhandapani
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.
摘要翻译：通过提供半导体衬底和具有侧壁的上覆控制电极来形成具有应变增强的半导体器件。在控制电极的侧壁附近形成绝缘层。注入半导体衬底和控制电极以形成第一和第二掺杂电流电极区域，第一和第二掺杂电流电极区域中的每一个的一部分被驱动以在第一和第二掺杂电流电极区域的沟道区域中的绝缘层和控制电极之下半导体器件。第一和第二掺杂电流电极区域除了在控制电极和绝缘层之下除去分别形成第一和第二沟槽的半导体衬底外。在第一和第二沟槽内形成有相对于半导体衬底具有不同晶格常数的原位掺杂材料，用作半导体器件的第一和第二电流电极。

7. 发明申请

US20070238250A1 Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor 失效
标题翻译：使用蚀刻停止层的半导体制造工艺来优化源极/漏极应力源的形成
公开(公告)号：US20070238250A1
公开(公告)日：2007-10-11
申请号：US11393340
申请日：2006-03-30
申请人： Da Zhang , Ted White , Bich-Yen Nguyen
发明人： Da Zhang , Ted White , Bich-Yen Nguyen
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/76254 , H01L21/76283 , H01L29/66772 , H01L29/78684
摘要： A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.
摘要翻译：半导体制造工艺包括形成覆盖掩埋氧化物（BOX）层和覆盖ESL的有源半导体层的蚀刻停止层（ESL）。形成覆盖有源半导体层的栅电极。蚀刻有源半导体层的源极/漏极区域以露出ESL。源极/漏极应力源在ESL上形成，其源极/漏极应力应变应变晶体管沟道。形成ESL可以包括外延生长厚度为约30nm或更小的硅锗ESL。优选地，有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。使用加热到约75℃温度的NH 4 OH：H 2 O 2的溶液进行湿蚀刻可以用于蚀刻源/漏区。 ESL可以是具有第一百分比的锗的硅锗。源极/漏极应力源可以是对于P型晶体管具有第二百分比的锗的硅锗，并且它们可以是N型晶体管的硅碳。

8. 发明申请

US20070215908A1 Electronic device including a semiconductor fin and a process for forming the electronic device 有权
标题翻译：包括半导体鳍片的电子设备和用于形成电子设备的工艺
公开(公告)号：US20070215908A1
公开(公告)日：2007-09-20
申请号：US11375894
申请日：2006-03-15
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66507 , H01L29/66795 , H01L29/78684
摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
摘要翻译：电子器件可以包括覆盖绝缘层的半导体鳍片。电子器件还可以包括覆盖半导体鳍片的半导体层。半导体层可以具有彼此间隔开的第一部分和第二部分。在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。电子器件还可以包括覆盖半导体层的金属 - 半导体层。在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

9. 发明申请

US20070184601A1 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20070184601A1
公开(公告)日：2007-08-09
申请号：US11349595
申请日：2006-02-08
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823814 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion over the dielectric, a first in situ doped semiconductor portion over the metal portion, and a first blocking cap over the in situ doped semiconductor portion. The method further includes performing implantations to form source/drain regions adjacent the first and second gate stack, where the first blocking cap has a thickness sufficient to substantially block implant dopants from entering the first in situ doped semiconductor portion. Source/drain embedded stressors are also formed.
摘要翻译：一种用于形成半导体器件的方法包括提供具有第一掺杂区域和第二掺杂区域的半导体衬底，在第一掺杂区域和第二掺杂区域上提供电介质，以及在电介质上至少形成第一栅极叠层第一掺杂区域的一部分。第一栅极堆叠包括电介质上的金属部分，金属部分上方的第一原位掺杂半导体部分以及原位掺杂半导体部分上的第一阻挡盖。该方法还包括执行注入以形成与第一和第二栅极堆叠相邻的源极/漏极区域，其中第一阻挡盖具有足以基本上阻挡注入掺杂剂进入第一原位掺杂半导体部分的厚度。源/漏嵌入式应力源也形成。

10. 发明授权

US07538002B2 Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors 失效
标题翻译：集成源极/漏极应力和半导体介电层应力的半导体工艺
公开(公告)号：US07538002B2
公开(公告)日：2009-05-26
申请号：US11361171
申请日：2006-02-24
申请人： Da Zhang , Vance H. Adams , Bich-Yen Nguyen , Paul A. Grudowski
发明人： Da Zhang , Vance H. Adams , Bich-Yen Nguyen , Paul A. Grudowski
IPC分类号： H01L21/336
CPC分类号： H01L29/7846 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.
摘要翻译：半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

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