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1. 发明授权

US08114717B2 Methods to shape the electric field in electron devices, passivate dislocations and point defects, and enhance the luminescence efficiency of optical devices 有权
标题翻译：在电子器件中形成电场的方法，钝化位错和点缺陷，提高光器件的发光效率
公开(公告)号：US08114717B2
公开(公告)日：2012-02-14
申请号：US11599874
申请日：2006-11-15
申请人： Tomas Palacios , Likun Shen , Umesh K. Mishra
发明人： Tomas Palacios , Likun Shen , Umesh K. Mishra
IPC分类号： H01L21/335
CPC分类号： H01L29/2003 , H01L29/207 , H01L29/402 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L33/0095
摘要： A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage. Three different methods to introduce dispersion in the 50 nm closest to the gate are described: (1) introduction of a small gap between the passivation and the gate metal, (2) gradually reducing the thickness of the passivation, and (3) gradually reducing the thickness of the AlGaN cap layer in the region close the gate.
摘要翻译：公开了可以在1,2或3维度的电子设备中形成电场分布的氟处理。还公开了通过将受控量的分散引入到器件中来增加AlGaN / GaN高电子迁移率晶体管的击穿电压的方法。该色散足够大以减少通道中的峰值电场，但是足够低以便不会导致器件的输出功率的显着降低。在该设计中，整个晶体管被钝化以抵消色散，除了在栅极的漏极侧旁边的50至100nm宽的小区域之外。在该区域中，表面捕集器产生有限的色散，这将扩散栅极边缘处的高电场，从而增加击穿电压。描述了在最接近栅极的50nm中引入色散的三种不同的方法：（1）在钝化和栅极金属之间引入小的间隙，（2）逐渐减小钝化的厚度，和（3）逐渐降低在关闭栅极的区域中的AlGaN覆盖层的厚度。

2. 发明申请

US20080116080A1 GATED ELECTRODES FOR ELECTROLYSIS AND ELECTROSYNTHESIS 有权
标题翻译：用于电解和电泳的电极
公开(公告)号：US20080116080A1
公开(公告)日：2008-05-22
申请号：US11943363
申请日：2007-11-20
申请人： Rakesh K. Lal , Likun Shen , Umesh K. Mishra
发明人： Rakesh K. Lal , Likun Shen , Umesh K. Mishra
IPC分类号： C25B1/00 , C25B11/00 , C25B9/00
CPC分类号： C25B1/003 , C25B11/0447 , Y02P20/135
摘要： A gated electrode structure for altering a potential and electric field in an electrolyte near at least one working electrode is disclosed. The gated electrode structure may comprise a gate electrode biased appropriately with respect to a working electrode. Applying an appropriate static or dynamic (time varying) gate potential relative to the working electrode modifies the electric potential and field in an interfacial region between the working electrode and the electrolyte, and increases electron emission to and from states in the electrolyte, thereby facilitating an electrochemical, electrolytic or electrosynthetic reaction and reducing electrode overvoltage/overpotential.
摘要翻译：公开了一种用于改变靠近至少一个工作电极的电解质中的电场和电场的选通电极结构。门电极结构可以包括相对于工作电极适当地偏置的栅电极。施加相对于工作电极的适当的静态或动态（时变）门电位改变了工作电极和电解质之间的界面区域中的电位和场，并且增加了电解质中的电子发射，从而促进了电化学，电解或电合成反应和还原电极过电压/超电势。

3. 发明申请

US20110156572A1 INTERDIGITATED MULTIPLE PIXEL ARRAYS OF LIGHT-EMITTING DEVICES 有权
标题翻译：间隔多个像素阵列的发光设备
公开(公告)号：US20110156572A1
公开(公告)日：2011-06-30
申请号：US13045148
申请日：2011-03-10
申请人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
发明人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
IPC分类号： H01J1/62 , H01J9/00
CPC分类号： H01L25/0753 , F21K9/00 , H01L27/156 , H01L33/08 , H01L33/14 , H01L33/20 , H01L33/38 , H01L33/385 , H01L33/42 , H01L33/486 , H01L33/62 , H01L33/64 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
摘要： The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
摘要翻译：本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。每个像素是具有尺寸l的边的正方形。通过增加像素的有源区域的周长来使串联电阻最小化。串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

4. 发明授权

US07911126B2 Interdigitated multiple pixel arrays of light-emitting devices 有权
标题翻译：交错的多个像素阵列的发光器件
公开(公告)号：US07911126B2
公开(公告)日：2011-03-22
申请号：US12419788
申请日：2009-04-07
申请人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
发明人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
IPC分类号： H01J1/62
CPC分类号： H01L25/0753 , F21K9/00 , H01L27/156 , H01L33/08 , H01L33/14 , H01L33/20 , H01L33/38 , H01L33/385 , H01L33/42 , H01L33/486 , H01L33/62 , H01L33/64 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
摘要： The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
摘要翻译：本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。每个像素是具有尺寸l的边的正方形。通过增加像素的有源区域的周长来使串联电阻最小化。串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

5. 发明授权

US08274206B2 Interdigitated multiple pixel arrays of light-emitting devices 有权
标题翻译：交错多个像素阵列的发光器件
公开(公告)号：US08274206B2
公开(公告)日：2012-09-25
申请号：US13045148
申请日：2011-03-10
申请人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
发明人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
IPC分类号： H01J1/62
CPC分类号： H01L25/0753 , F21K9/00 , H01L27/156 , H01L33/08 , H01L33/14 , H01L33/20 , H01L33/38 , H01L33/385 , H01L33/42 , H01L33/486 , H01L33/62 , H01L33/64 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
摘要： The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
摘要翻译：本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。每个像素是具有尺寸l的边的正方形。通过增加像素的有源区域的周长来使串联电阻最小化。串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

6. 发明申请

US20090230411A1 INTERDIGITATED MULTIPLE PIXEL ARRAYS OF LIGHT-EMITTING DEVICES 有权
标题翻译：间隔多个像素阵列的发光设备
公开(公告)号：US20090230411A1
公开(公告)日：2009-09-17
申请号：US12419788
申请日：2009-04-07
申请人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
发明人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
IPC分类号： H01L33/00
CPC分类号： H01L25/0753 , F21K9/00 , H01L27/156 , H01L33/08 , H01L33/14 , H01L33/20 , H01L33/38 , H01L33/385 , H01L33/42 , H01L33/486 , H01L33/62 , H01L33/64 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
摘要： The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
摘要翻译：本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。每个像素是具有尺寸l的边的正方形。通过增加像素的有源区域的周长来使串联电阻最小化。串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

7. 发明授权

US07518305B2 Interdigitated multi-pixel arrays for the fabrication of light-emitting devices with very low series-resistances and improved heat-sinking 有权
标题翻译：用于制造具有非常低的串联电阻和改进的散热的发光器件的叉指多像素阵列
公开(公告)号：US07518305B2
公开(公告)日：2009-04-14
申请号：US11264794
申请日：2005-11-01
申请人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
发明人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
IPC分类号： H01J1/62
CPC分类号： H01L25/0753 , F21K9/00 , H01L27/156 , H01L33/08 , H01L33/14 , H01L33/20 , H01L33/38 , H01L33/385 , H01L33/42 , H01L33/486 , H01L33/62 , H01L33/64 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
摘要： The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
摘要翻译：本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。每个像素是具有尺寸l的边的正方形。通过增加像素的有源区域的周长来使串联电阻最小化。串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

8. 发明授权

US09496353B2 Fabrication of single or multiple gate field plates 有权
标题翻译：制造单栅极或多栅极场板
公开(公告)号：US09496353B2
公开(公告)日：2016-11-15
申请号：US12898341
申请日：2010-10-05
申请人： Alessandro Chini , Umesh K. Mishra , Primit Parikh , Yifeng Wu
发明人： Alessandro Chini , Umesh K. Mishra , Primit Parikh , Yifeng Wu
IPC分类号： H01L29/40 , H01L27/06 , H01L29/423 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/207 , H01L29/417 , H01L29/78
CPC分类号： H01L29/404 , H01L27/0605 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/401 , H01L29/402 , H01L29/41766 , H01L29/42312 , H01L29/42316 , H01L29/66462 , H01L29/7787 , H01L29/785
摘要： A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
摘要翻译：使用在场效应晶体管的表面上的介电材料沉积/生长，介电材料蚀刻和金属蒸发的连续步骤来制造单栅极或多栅极场板的工艺。这种制造工艺允许对场板操作的严格控制，因为介电材料沉积/生长通常是良好可控的工艺。此外，沉积在器件表面上的电介质材料不需要从器件本征区域去除：这基本上使得能够实现电镀设备，而不需要低损耗介电材料干/湿蚀刻。使用多个栅极场板还通过多个连接降低栅极电阻，从而提高大的周边和/或亚微米栅极器件的性能。

9. 发明授权

US09129977B2 Method of controlling stress in group-III nitride films deposited on substrates 有权
标题翻译：控制沉积在衬底上的III族氮化物膜的应力的方法
公开(公告)号：US09129977B2
公开(公告)日：2015-09-08
申请号：US13306763
申请日：2011-11-29
申请人： Hugues Marchand , Brendan J. Moran , Umesh K. Mishra , James S. Speck
发明人： Hugues Marchand , Brendan J. Moran , Umesh K. Mishra , James S. Speck
IPC分类号： H01L33/32 , H01L29/267 , H01L23/00 , C30B25/02 , C30B29/40 , H01L21/02 , H01L33/00 , H01L29/20 , H01L29/205 , H01L33/12
CPC分类号： H01L23/562 , C30B25/02 , C30B29/403 , C30B29/406 , H01L21/02378 , H01L21/02381 , H01L21/02458 , H01L21/0251 , H01L21/0254 , H01L21/0262 , H01L29/2003 , H01L29/205 , H01L33/0025 , H01L33/0066 , H01L33/0075 , H01L33/12 , H01L33/32 , H01L2924/0002 , H01L2924/00
摘要： Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
摘要翻译：公开了控制沉积在硅和碳化硅衬底上的GaN膜中的应力控制方法和由其制备的膜。典型的方法包括提供衬底并在衬底上沉积梯度的氮化镓层，其具有基本上连续等级的从初始组成到由生长室中的至少一种前体的供应形成的最终组成的变化的组成，而不会中断在供应。典型的半导体膜包括沉积在衬底上的衬底和梯度的氮化镓层，其具有从初始组成到最终组成的基本连续等级的变化的组成，其由在生长室中供应至少一种前体而形成，而不会中断在供应。

10. 发明授权

US08324637B2 High efficiency LEDs with tunnel junctions 有权
标题翻译：具有隧道结的高效率LED
公开(公告)号：US08324637B2
公开(公告)日：2012-12-04
申请号：US12782107
申请日：2010-05-18
申请人： James P. Ibbetson , Bernd P. Keller , Umesh K. Mishra
发明人： James P. Ibbetson , Bernd P. Keller , Umesh K. Mishra
IPC分类号： H01L27/15
CPC分类号： H01L33/04 , H01L33/0016 , H01L33/08 , H01L33/32
摘要： An LED made from a wide band gap semiconductor material and having a low resistance p-type confinement layer with a tunnel junction in a wide band gap semiconductor device is disclosed. A dissimilar material is placed at the tunnel junction where the material generates a natural dipole. This natural dipole is used to form a junction having a tunnel width that is smaller than such a width would be without the dissimilar material. A low resistance p-type confinement layer having a tunnel junction in a wide band gap semiconductor device may be fabricated by generating a polarization charge in the junction of the confinement layer, and forming a tunnel width in the junction that is smaller than the width would be without the polarization charge. Tunneling through the tunnel junction in the confinement layer may be enhanced by the addition of impurities within the junction. These impurities may form band gap states in the junction.
摘要翻译：公开了一种由宽带隙半导体材料制成的LED，并具有在宽带隙半导体器件中具有隧道结的低电阻p型约束层。不同的材料放置在材料产生天然偶极子的隧道结处。该天然偶极子用于形成隧道宽度小于不具有不同材料的宽度的接合点。在宽带隙半导体器件中具有隧道结的低电阻p型限制层可以通过在限制层的接合处产生极化电荷并在接合部中形成小于宽度的隧道宽度来制造没有极化电荷。可以通过在连接处添加杂质来增强通过限制层中的隧道结的隧穿。这些杂质可能在结中形成带隙状态。

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