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1. 发明授权

US08237198B2 Semiconductor heterostructure diodes 有权
标题翻译：半导体异质结二极管
公开(公告)号：US08237198B2
公开(公告)日：2012-08-07
申请号：US13008874
申请日：2011-01-18
申请人： Yifeng Wu , Rongming Chu , Primit Parikh , Umesh Mishra , Ilan Ben-Yaacov , Likun Shen
发明人： Yifeng Wu , Rongming Chu , Primit Parikh , Umesh Mishra , Ilan Ben-Yaacov , Likun Shen
IPC分类号： H01L33/00 , H01L29/739
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

2. 发明申请

US20050077541A1 GaN/AIGaN/GaN dispersion-free high electron mobility transistors 失效
标题翻译： GaN / AIGaN /无GaN分散体的高电子迁移率晶体管
公开(公告)号：US20050077541A1
公开(公告)日：2005-04-14
申请号：US10962911
申请日：2004-10-12
申请人： Likun Shen , Sten Heikman , Umesh Mishra
发明人： Likun Shen , Sten Heikman , Umesh Mishra
IPC分类号： H01L21/335 , H01L29/20 , H01L29/778 , H01L29/739
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/7787
摘要： A dispersion-free high electron mobility transistor (HEMT), comprised of a substrate; a semi-insulating buffer layer, comprised of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), deposited on the substrate, an AlGaN barrier layer, with an aluminum (Al) mole fraction larger than that of the semi-insulating buffer layer, deposited on the semi-insulating buffer layer, an n-type doped graded AlGaN layer deposited on the AlGaN barrier layer, wherein an Al mole fraction is decreased from a bottom of the n-type doped graded AlGaN layer to a top of the n-type doped graded AlGaN layer, and a cap layer, comprised of GaN or AlGaN with an Al mole fraction smaller than that of the AlGaN barrier layer, deposited on the n-type doped graded AlGaN layer.
摘要翻译：一种无分散的高电子迁移率晶体管（HEMT），由衬底组成; 沉积在衬底上的由氮化镓（GaN）或氮化镓铝（AlGaN）组成的半绝缘缓冲层，具有大于半绝缘缓冲层的铝（Al）摩尔分数的AlGaN阻挡层沉积在半绝缘缓冲层上的沉积在AlGaN阻挡层上的n型掺杂的梯度AlGaN层，其中Al掺杂分数从n型掺杂的梯度AlGaN层的底部减少到n的顶部型Al掺杂分级AlGaN层，以及由Al或AlGaN构成的覆盖层，其Al分压比AlGaN阻挡层的Al摩尔分数小，形成在n型掺杂的梯度AlGaN层上。

3. 发明授权

US08114717B2 Methods to shape the electric field in electron devices, passivate dislocations and point defects, and enhance the luminescence efficiency of optical devices 有权
标题翻译：在电子器件中形成电场的方法，钝化位错和点缺陷，提高光器件的发光效率
公开(公告)号：US08114717B2
公开(公告)日：2012-02-14
申请号：US11599874
申请日：2006-11-15
申请人： Tomas Palacios , Likun Shen , Umesh K. Mishra
发明人： Tomas Palacios , Likun Shen , Umesh K. Mishra
IPC分类号： H01L21/335
CPC分类号： H01L29/2003 , H01L29/207 , H01L29/402 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L33/0095
摘要： A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage. Three different methods to introduce dispersion in the 50 nm closest to the gate are described: (1) introduction of a small gap between the passivation and the gate metal, (2) gradually reducing the thickness of the passivation, and (3) gradually reducing the thickness of the AlGaN cap layer in the region close the gate.
摘要翻译：公开了可以在1,2或3维度的电子设备中形成电场分布的氟处理。还公开了通过将受控量的分散引入到器件中来增加AlGaN / GaN高电子迁移率晶体管的击穿电压的方法。该色散足够大以减少通道中的峰值电场，但是足够低以便不会导致器件的输出功率的显着降低。在该设计中，整个晶体管被钝化以抵消色散，除了在栅极的漏极侧旁边的50至100nm宽的小区域之外。在该区域中，表面捕集器产生有限的色散，这将扩散栅极边缘处的高电场，从而增加击穿电压。描述了在最接近栅极的50nm中引入色散的三种不同的方法：（1）在钝化和栅极金属之间引入小的间隙，（2）逐渐减小钝化的厚度，和（3）逐渐降低在关闭栅极的区域中的AlGaN覆盖层的厚度。

4. 发明授权

US07898004B2 Semiconductor heterostructure diodes 有权
标题翻译：半导体异质结二极管
公开(公告)号：US07898004B2
公开(公告)日：2011-03-01
申请号：US12332284
申请日：2008-12-10
申请人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
发明人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
IPC分类号： H01L29/739 , H01L33/00
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

5. 发明申请

US20080116080A1 GATED ELECTRODES FOR ELECTROLYSIS AND ELECTROSYNTHESIS 有权
标题翻译：用于电解和电泳的电极
公开(公告)号：US20080116080A1
公开(公告)日：2008-05-22
申请号：US11943363
申请日：2007-11-20
申请人： Rakesh K. Lal , Likun Shen , Umesh K. Mishra
发明人： Rakesh K. Lal , Likun Shen , Umesh K. Mishra
IPC分类号： C25B1/00 , C25B11/00 , C25B9/00
CPC分类号： C25B1/003 , C25B11/0447 , Y02P20/135
摘要： A gated electrode structure for altering a potential and electric field in an electrolyte near at least one working electrode is disclosed. The gated electrode structure may comprise a gate electrode biased appropriately with respect to a working electrode. Applying an appropriate static or dynamic (time varying) gate potential relative to the working electrode modifies the electric potential and field in an interfacial region between the working electrode and the electrolyte, and increases electron emission to and from states in the electrolyte, thereby facilitating an electrochemical, electrolytic or electrosynthetic reaction and reducing electrode overvoltage/overpotential.
摘要翻译：公开了一种用于改变靠近至少一个工作电极的电解质中的电场和电场的选通电极结构。门电极结构可以包括相对于工作电极适当地偏置的栅电极。施加相对于工作电极的适当的静态或动态（时变）门电位改变了工作电极和电解质之间的界面区域中的电位和场，并且增加了电解质中的电子发射，从而促进了电化学，电解或电合成反应和还原电极过电压/超电势。

6. 发明申请

US20070224710A1 Methods to shape the electric field in electron devices, passivate dislocations and point defects, and enhance the luminescence efficiency of optical devices 有权
标题翻译：在电子器件中形成电场的方法，钝化位错和点缺陷，提高光器件的发光效率
公开(公告)号：US20070224710A1
公开(公告)日：2007-09-27
申请号：US11599874
申请日：2006-11-15
申请人： Tomas Palacios , Likun Shen , Umesh Mishra
发明人： Tomas Palacios , Likun Shen , Umesh Mishra
IPC分类号： H01L21/00 , H01L21/335
CPC分类号： H01L29/2003 , H01L29/207 , H01L29/402 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L33/0095
摘要： A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage. Three different methods to introduce dispersion in the 50 nm closest to the gate are described: (1) introduction of a small gap between the passivation and the gate metal, (2) gradually reducing the thickness of the passivation, and (3) gradually reducing the thickness of the AlGaN cap layer in the region close the gate.
摘要翻译：公开了可以在1,2或3维度的电子设备中形成电场分布的氟处理。还公开了通过将受控量的分散引入到器件中来增加AlGaN / GaN高电子迁移率晶体管的击穿电压的方法。该色散足够大以减少通道中的峰值电场，但是足够低以便不会导致器件的输出功率的显着降低。在该设计中，整个晶体管被钝化以抵消色散，除了在栅极的漏极侧旁边的50至100nm宽的小区域之外。在该区域中，表面捕集器产生有限的色散，这将扩散栅极边缘处的高电场，从而增加击穿电压。描述了在最接近栅极的50nm中引入色散的三种不同的方法：（1）在钝化和栅极金属之间引入小的间隙，（2）逐渐减小钝化的厚度，和（3）逐渐降低在关闭栅极的区域中的AlGaN覆盖层的厚度。

7. 发明授权

US08147659B2 Gated electrodes for electrolysis and electrosynthesis 有权
标题翻译：用于电解和电合成的门电极
公开(公告)号：US08147659B2
公开(公告)日：2012-04-03
申请号：US11943363
申请日：2007-11-20
申请人： Rakesh K. Lal , Likun Shen , Umesh Kumar Mishra
发明人： Rakesh K. Lal , Likun Shen , Umesh Kumar Mishra
IPC分类号： C25B9/04 , C25D17/00
CPC分类号： C25B1/003 , C25B11/0447 , Y02P20/135
摘要： A gated electrode structure for altering a potential and electric field in an electrolyte near at least one working electrode is disclosed. The gated electrode structure may comprise a gate electrode biased appropriately with respect to a working electrode. Applying an appropriate static or dynamic (time varying) gate potential relative to the working electrode modifies the electric potential and field in an interfacial region between the working electrode and the electrolyte, and increases electron emission to and from states in the electrolyte, thereby facilitating an electrochemical, electrolytic or electrosynthetic reaction and reducing electrode overvoltage/overpotential.
摘要翻译：公开了一种用于改变靠近至少一个工作电极的电解质中的电场和电场的选通电极结构。门电极结构可以包括相对于工作电极适当地偏置的栅电极。施加相对于工作电极的适当的静态或动态（时变）门电位改变了工作电极和电解质之间的界面区域中的电位和场，并且增加了电解质中的电子发射，从而促进了电化学，电解或电合成反应和还原电极过电压/超电势。

8. 发明申请

US20110156572A1 INTERDIGITATED MULTIPLE PIXEL ARRAYS OF LIGHT-EMITTING DEVICES 有权
标题翻译：间隔多个像素阵列的发光设备
公开(公告)号：US20110156572A1
公开(公告)日：2011-06-30
申请号：US13045148
申请日：2011-03-10
申请人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
发明人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
IPC分类号： H01J1/62 , H01J9/00
CPC分类号： H01L25/0753 , F21K9/00 , H01L27/156 , H01L33/08 , H01L33/14 , H01L33/20 , H01L33/38 , H01L33/385 , H01L33/42 , H01L33/486 , H01L33/62 , H01L33/64 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
摘要： The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
摘要翻译：本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。每个像素是具有尺寸l的边的正方形。通过增加像素的有源区域的周长来使串联电阻最小化。串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

9. 发明授权

US07911126B2 Interdigitated multiple pixel arrays of light-emitting devices 有权
标题翻译：交错的多个像素阵列的发光器件
公开(公告)号：US07911126B2
公开(公告)日：2011-03-22
申请号：US12419788
申请日：2009-04-07
申请人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
发明人： Arpan Chakraborty , Likun Shen , Umesh K. Mishra
IPC分类号： H01J1/62
CPC分类号： H01L25/0753 , F21K9/00 , H01L27/156 , H01L33/08 , H01L33/14 , H01L33/20 , H01L33/38 , H01L33/385 , H01L33/42 , H01L33/486 , H01L33/62 , H01L33/64 , H01L2924/0002 , H01L2933/0033 , H01L2933/0066 , H01L2924/00
摘要： The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.
摘要翻译：本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。每个像素是具有尺寸l的边的正方形。通过增加像素的有源区域的周长来使串联电阻最小化。串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

10. 发明申请

US20090267078A1 Enhancement Mode III-N HEMTs 有权
标题翻译：增强模式III-N HEMTs
公开(公告)号：US20090267078A1
公开(公告)日：2009-10-29
申请号：US12108449
申请日：2008-04-23
申请人： Umesh Mishra , Robert Coffie , Likun Shen , Ilan Ben-Yaacov , Primit Parikh
发明人： Umesh Mishra , Robert Coffie , Likun Shen , Ilan Ben-Yaacov , Primit Parikh
IPC分类号： H01L29/778 , H01L21/338
CPC分类号： H01L29/7784 , H01L21/0217 , H01L21/0254 , H01L29/0847 , H01L29/1033 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/365 , H01L29/4236 , H01L29/518 , H01L29/66431 , H01L29/66462 , H01L29/7783 , H01L29/7787 , H01L29/7788
摘要： A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.
摘要翻译：一种III-N半导体器件，其包括衬底和包括部分在栅极区域下方的区域的氮化物沟道层，以及在栅极下方的部分的相对侧上的两个沟道存取区域。通道接入区域可以在与栅极下方的区域不同的层中。该器件包括与沟道层相邻的AlXN层，其中X是镓，铟或它们的组合，以及在与沟道接入区相邻的区域中与AlXN层相邻的优选n掺杂GaN层。选择AlXN层中的Al的浓度，n掺杂GaN层中的AlXN层厚度和n掺杂浓度，以在沟道接入区域中引起2DEG电荷，而不在栅极下方引起任何实质的2DEG电荷，使得在没有施加到栅极的开关电压的情况下，通道不导通。

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