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    • 1. 发明授权
    • Method for manufacturing thin film transistor substrate
    • 薄膜晶体管基板的制造方法
    • US08481373B2
    • 2013-07-09
    • US13383220
    • 2010-03-16
    • Tohru OkabeHirohiko NishikiYoshimasa ChikamaTakeshi Hara
    • Tohru OkabeHirohiko NishikiYoshimasa ChikamaTakeshi Hara
    • H01L21/336
    • H01L29/7869G02F1/1368H01L27/1225H01L27/124H01L27/1248H01L29/42384
    • A method for manufacturing a thin film transistor substrate includes a step of forming a gate electrode (11a) and a first interconnect on a substrate (10), a step of forming a gate insulating film (12a) having a contact hole at a position overlapping the first interconnect, a step of forming a source electrode (13a) and a drain electrode (13b) overlapping the gate electrode (11a) and separated apart from each other, and a second interconnect connected via the contact hole to the first interconnect, a step of successively forming an oxide semiconductor film (14) and a second insulating film (15), and thereafter, patterning the second insulating film (15) to form an interlayer insulating film (15a), and a step of reducing the resistance of the oxide semiconductor film (14) exposed through the interlayer insulating film (15a) to form a pixel electrode (14b).
    • 制造薄膜晶体管基板的方法包括在基板(10)上形成栅极(11a)和第一布线的步骤,在重叠的位置形成具有接触孔的栅极绝缘膜(12a)的步骤 所述第一互连,形成与所述栅电极(11a)重叠并分离的源电极(13a)和漏电极(13b)的步骤,以及经由所述接触孔与所述第一互连件连接的第二互连件, 连续地形成氧化物半导体膜(14)和第二绝缘膜(15)的步骤,然后对第二绝缘膜(15)进行图案化以形成层间绝缘膜(15a),并且降低 氧化物半导体膜(14)通过层间绝缘膜(15a)露出以形成像素电极(14b)。
    • 2. 发明申请
    • METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE
    • 制造薄膜晶体管基板的方法
    • US20120108018A1
    • 2012-05-03
    • US13383220
    • 2010-03-16
    • Tohru OkabeHirohiko NishikiYoshimasa ChikamaTakeshi Hara
    • Tohru OkabeHirohiko NishikiYoshimasa ChikamaTakeshi Hara
    • H01L21/336
    • H01L29/7869G02F1/1368H01L27/1225H01L27/124H01L27/1248H01L29/42384
    • A method for manufacturing a thin film transistor substrate includes a step of forming a gate electrode (11a) and a first interconnect on a substrate (10), a step of forming a gate insulating film (12a) having a contact hole at a position overlapping the first interconnect, a step of forming a source electrode (13a) and a drain electrode (13b) overlapping the gate electrode (11a) and separated apart from each other, and a second interconnect connected via the contact hole to the first interconnect, a step of successively forming an oxide semiconductor film (14) and a second insulating film (15), and thereafter, patterning the second insulating film (15) to form an interlayer insulating film (15a), and a step of reducing the resistance of the oxide semiconductor film (14) exposed through the interlayer insulating film (15a) to form a pixel electrode (14b).
    • 制造薄膜晶体管基板的方法包括在基板(10)上形成栅极(11a)和第一布线的步骤,在重叠的位置形成具有接触孔的栅极绝缘膜(12a)的步骤 所述第一互连,形成与所述栅电极(11a)重叠并分离的源电极(13a)和漏电极(13b)的步骤,以及经由所述接触孔与所述第一互连件连接的第二互连件, 连续地形成氧化物半导体膜(14)和第二绝缘膜(15)的步骤,然后对第二绝缘膜(15)进行图案化以形成层间绝缘膜(15a),并且降低 氧化物半导体膜(14)通过层间绝缘膜(15a)露出以形成像素电极(14b)。
    • 5. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    • 半导体器件及其制造方法
    • US20120199891A1
    • 2012-08-09
    • US13499960
    • 2010-10-04
    • Masahiko SuzukiHirohiko NishikiYoshimasa ChikamaYoshifumi OhtaTetsuya AitaOkifumi NakagawaTakeshi Hara
    • Masahiko SuzukiHirohiko NishikiYoshimasa ChikamaYoshifumi OhtaTetsuya AitaOkifumi NakagawaTakeshi Hara
    • H01L29/78H01L21/336
    • H01L29/7869G02F1/1368H01L29/66969H01L29/78606
    • A semiconductor device includes: a gate electrode (3) arranged on a substrate (1); a gate insulating layer (5) deposited over the gate electrode (3); an island of an oxide semiconductor layer (7) formed on the gate insulating layer (5) and including a channel region (7c) and first and second contact regions (7s, 7d) located on right- and left-hand sides of the channel region (7c); a source electrode (11) electrically connected to the first contact region (7s); a drain electrode (13) electrically connected to the second contact region (7d); and a protective layer (9) which is arranged on, and in contact with, the oxide semiconductor layer (7). The protective layer (9) covers the channel region (7c) on the surface of the oxide semiconductor layer (7), the sidewalls (7e) thereof located in a channel width direction with respect to the channel region (7c), and other portions (7f) thereof between the channel region (7c) and the sidewalls (7e). As a result, the hysteresis characteristic of a TFT that uses an oxide semiconductor can be improved and its reliability can be increased.
    • 半导体器件包括:布置在衬底(1)上的栅电极(3); 沉积在栅电极(3)上的栅极绝缘层(5); 形成在所述栅极绝缘层(5)上并且包括沟道区(7c)的氧化物半导体层(7)的岛和位于所述沟道的右侧和左侧的第一和第二接触区(7s,7d) 区域(7c); 电连接到第一接触区域(7s)的源电极(11); 电连接到第二接触区域(7d)的漏电极(13); 以及设置在所述氧化物半导体层(7)上并与所述氧化物半导体层(7)接触的保护层(9)。 保护层(9)覆盖氧化物半导体层(7)的表面上的沟道区域(7c),其侧壁(7e)相对于沟道区域(7c)位于沟道宽度方向,其它部分 (7f)之间的沟道区域(7f)。 结果,可以提高使用氧化物半导体的TFT的滞后特性,并且可以提高其可靠性。
    • 9. 发明授权
    • Semiconductor device and method for producing same
    • 半导体装置及其制造方法
    • US08685803B2
    • 2014-04-01
    • US13514081
    • 2010-12-03
    • Yoshimasa ChikamaHirohiko NishikiYoshifumi OhtaTakeshi HaraTetsuya AitaMasahiko SuzukiMichiko TakeiOkifumi NakagawaYoshiyuki HarumotoHinae Mizuno
    • Yoshimasa ChikamaHirohiko NishikiYoshifumi OhtaYuuji MizunoTakeshi HaraTetsuya AitaMasahiko SuzukiMichiko TakeiOkifumi NakagawaYoshiyuki Harumoto
    • H01L21/00
    • H01L27/1225G02F1/13458G02F1/136213H01L27/124H01L27/1244H01L27/1248
    • A semiconductor device includes: a thin film transistor having a gate line (3a), a first insulating film (5), an island-shaped oxide semiconductor layer (7a), a second insulating film (9), a source line (13as), a drain electrode (13ad), and a passivation film; and a terminal portion having a first connecting portion (3c) made of the same conductive film as the gate line, a second connecting portion (13c) made of the same conductive film as the source line and the drain electrode, and a third connecting portion (19c) formed on the second connecting portion. The second connecting portion is in contact with the first connecting portion within a first opening (11c) provided in the first and second insulating films; the third connecting portion (19c) is in contact with the second connecting portion within a second opening (17c) provided in the passivation film; and the second connecting portion (13c) covers end faces of the first and second insulating films within the first opening (11c), but does not cover an end face of the passivation film (15) within the second opening (17c). As a result, the taper shape of a contact hole of the terminal portion can be controlled with a high precision.
    • 半导体器件包括:具有栅极线(3a),第一绝缘膜(5),岛状氧化物半导体层(7a),第二绝缘膜(9),源极线(13as))的薄膜晶体管, ,漏电极(13ad)和钝化膜; 以及具有由与栅极线相同的导电膜制成的第一连接部分(3c)的端子部分,由与源极线和漏极电极相同的导电膜制成的第二连接部分(13c)和第三连接部分 (19c)形成在第二连接部分上。 第二连接部分在设置在第一和第二绝缘膜中的第一开口(11c)内与第一连接部分接触; 所述第三连接部分(19c)在设置在所述钝化膜中的第二开口(17c)内与所述第二连接部分接触; 并且所述第二连接部分(13c)覆盖所述第一开口(11c)内的所述第一绝缘膜和所述第二绝缘膜的端面,但不覆盖所述第二开口(17c)内的所述钝化膜(15)的端面。 结果,可以高精度地控制端子部分的接触孔的锥形形状。