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1. 发明申请

US20090243114A1 Densely packed metal segments patterned in a semiconductor die 有权
标题翻译：图案化在半导体芯片中的密集金属片段
公开(公告)号：US20090243114A1
公开(公告)日：2009-10-01
申请号：US11112194
申请日：2005-04-22
申请人： Tinghao F. Wang , Dieter Dornisch , Julia M. Wu , Hadi Abdul-Ridha , David J. Howard
发明人： Tinghao F. Wang , Dieter Dornisch , Julia M. Wu , Hadi Abdul-Ridha , David J. Howard
IPC分类号： H01L23/48
CPC分类号： H01L21/02071 , H01L21/32136 , H01L21/76885 , Y10S438/942 , Y10S438/945
摘要： A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.
摘要翻译：在半导体管芯中图案化金属层的方法包括在金属层上形成掩模以限定开放区域和致密区域。该方法还包括以第一蚀刻速率蚀刻金属层以在开放区域中形成多个金属段，并以第二蚀刻速率蚀刻金属层，以在致密区域中形成多个金属段，其中第一蚀刻速率近似等于第二蚀刻速率。该方法还包括执行多个带/钝化循环以去除在致密区域中金属段的侧壁上形成的聚合物。致密区域中的金属段的侧壁基本上不会发生底切，并且在致密区域中的金属段的侧壁上除去残留物。

2. 发明授权

US07709949B2 Densely packed metal segments patterned in a semiconductor die 有权
标题翻译：图案化在半导体芯片中的密集金属片段
公开(公告)号：US07709949B2
公开(公告)日：2010-05-04
申请号：US11112194
申请日：2005-04-22
申请人： Tinghao F. Wang , Dieter Dornisch , Julia M. Wu , Hadi Abdul-Ridha , David J. Howard
发明人： Tinghao F. Wang , Dieter Dornisch , Julia M. Wu , Hadi Abdul-Ridha , David J. Howard
IPC分类号： H01L23/48
CPC分类号： H01L21/02071 , H01L21/32136 , H01L21/76885 , Y10S438/942 , Y10S438/945
摘要： A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.
摘要翻译：在半导体管芯中图案化金属层的方法包括在金属层上形成掩模以限定开放区域和致密区域。该方法还包括以第一蚀刻速率蚀刻金属层以在开放区域中形成多个金属段，并以第二蚀刻速率蚀刻金属层，以在致密区域中形成多个金属段，其中第一蚀刻速率近似等于第二蚀刻速率。该方法还包括执行多个带/钝化循环以去除在致密区域中金属段的侧壁上形成的聚合物。致密区域中的金属段的侧壁基本上不会发生底切，并且在致密区域中的金属段的侧壁上除去残留物。

3. 发明授权

US06919272B2 Method for patterning densely packed metal segments in a semiconductor die and related structure 有权
标题翻译：图案化半导体管芯中紧密堆积的金属段和相关结构的方法
公开(公告)号：US06919272B2
公开(公告)日：2005-07-19
申请号：US10356447
申请日：2003-02-01
申请人： Tinghao F. Wang , Dieter Dornisch , Julia M. Wu , Hadi Abdul-Ridha , David J. Howard
发明人： Tinghao F. Wang , Dieter Dornisch , Julia M. Wu , Hadi Abdul-Ridha , David J. Howard
IPC分类号： H01L21/02 , H01L21/3205 , H01L21/3213 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02071 , H01L21/32136 , H01L21/76885 , Y10S438/942 , Y10S438/945
摘要： A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.
摘要翻译：在半导体管芯中图案化金属层的方法包括在金属层上形成掩模以限定开放区域和致密区域。该方法还包括以第一蚀刻速率蚀刻金属层以在开放区域中形成多个金属段，并以第二蚀刻速率蚀刻金属层，以在致密区域中形成多个金属段，其中第一蚀刻速率近似等于第二蚀刻速率。该方法还包括执行多个带/钝化循环以去除在致密区域中金属段的侧壁上形成的聚合物。致密区域中的金属段的侧壁基本上不会发生底切，并且在致密区域中的金属段的侧壁上除去残留物。

4. 发明授权

US07268038B2 Method for fabricating a MIM capacitor having increased capacitance density and related structure 有权
标题翻译：具有增加的电容密度和相关结构的MIM电容器的制造方法
公开(公告)号：US07268038B2
公开(公告)日：2007-09-11
申请号：US10997638
申请日：2004-11-23
申请人： Dieter Dornisch , Kenneth M. Ring , Tinghao F. Wang , David Howard , Guangming Li
发明人： Dieter Dornisch , Kenneth M. Ring , Tinghao F. Wang , David Howard , Guangming Li
IPC分类号： H01L21/8242
CPC分类号： H01L28/40
摘要： According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um2.
摘要翻译：根据本发明的一个实施例，在半导体管芯中制造MIM电容器的方法包括沉积第一互连金属层的步骤。该方法还包括在第一互连层上沉积氮化硅层。氮化硅层在沉积过程中使用至少12.5的氨 - 硅烷比沉积。该方法还包括在氮化硅层上沉积MIM电容器金属层。该方法还包括蚀刻MIM电容器金属层以形成MIM电容器的上电极。根据该示例性实施例，该方法还包括蚀刻氮化硅层以形成MIM电容器电介质段并蚀刻第一互连金属层以形成MIM电容器的下电极。 MIM电容器具有至少2.0fF / um 2的电容密度。

5. 发明授权

US07772673B1 Deep trench isolation and method for forming same 有权
标题翻译：深沟槽隔离及其形成方法
公开(公告)号：US07772673B1
公开(公告)日：2010-08-10
申请号：US11724916
申请日：2007-03-16
申请人： Kevin Q. Yin , Amol Kalburge , David J. Howard , Arjun Kar-Roy , Dieter Dornisch
发明人： Kevin Q. Yin , Amol Kalburge , David J. Howard , Arjun Kar-Roy , Dieter Dornisch
IPC分类号： H01L21/04
CPC分类号： H01L29/0692 , H01L21/763 , H01L29/66272 , H01L29/732
摘要： According to one exemplary embodiment, a semiconductor die including at least one deep trench isolation region for isolating an electronic device (for example, a bipolar device) includes a trench situated in a substrate of the semiconductor die, where the trench has sides surrounding the electronic device, and where the trench has at least one trench chamfered corner formed between and connecting the sides of the trench. The at least one trench chamferred corner is formed between a chamfered corner of an outside wall of said trench and a corner of an inside wall of the trench. A trench corner width at the at least one trench chamfered corner is less than a trench side width along the sides of the trench.
摘要翻译：根据一个示例性实施例，包括用于隔离电子器件（例如，双极器件）的至少一个深沟槽隔离区域的半导体管芯包括位于半导体管芯的衬底中的沟槽，其中沟槽具有围绕电子器件器件，并且其中沟槽具有形成在沟槽的侧面之间并连接沟槽的侧面的至少一个沟槽倒角。所述至少一个沟槽倒角形成在所述沟槽的外壁的倒角角和沟槽的内壁的角部之间。在至少一个沟槽倒角处的沟槽角宽度小于沿着沟槽的侧面的沟槽侧宽度。

6. 发明授权

US06885056B1 High-k dielectric stack in a MIM capacitor and method for its fabrication 有权
标题翻译： MIM电容器中的高k电介质堆叠及其制造方法
公开(公告)号：US06885056B1
公开(公告)日：2005-04-26
申请号：US10692431
申请日：2003-10-22
申请人： Dieter Dornisch , David J Howard , Abhijit B Joshi
发明人： Dieter Dornisch , David J Howard , Abhijit B Joshi
IPC分类号： H01L21/02 , H01L21/316 , H01L21/318 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/022 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/0228 , H01L21/31612 , H01L21/31616 , H01L21/31637 , H01L21/31641 , H01L21/3185 , H01L28/40 , H01L28/56 , H01L28/75
摘要： According to one exemplary embodiment, a high-k dielectric stack situated between upper and lower electrodes of a MIM capacitor comprises a first high-k dielectric layer, where the first high-k dielectric layer has a first dielectric constant. The high-k dielectric stack further comprises an intermediate dielectric layer situated on the first high-k dielectric layer, where the intermediate dielectric layer has a second dielectric constant. According to this exemplary embodiment, the high-k dielectric stack further comprises a second high-k dielectric layer situated on the intermediate dielectric layer, where the second high-k dielectric layer has a third dielectric constant. The second dielectric constant can be lower than the first dielectric constant and the third dielectric constant. The high-k dielectric stack further comprises first and second cladding layers, where the first cladding layer is situated underneath the first high-k dielectric layer and the second cladding layer is situated on the second high-k dielectric layer.
摘要翻译：根据一个示例性实施例，位于MIM电容器的上电极和下电极之间的高k电介质堆叠包括第一高k电介质层，其中第一高k电介质层具有第一介电常数。高k电介质堆叠还包括位于第一高k电介质层上的中间电介质层，其中中间介电层具有第二介电常数。根据该示例性实施例，高k电介质堆叠还包括位于中间介电层上的第二高k电介质层，其中第二高k电介质层具有第三介电常数。第二介电常数可以低于第一介电常数和第三介电常数。高k电介质堆叠还包括第一和第二覆层，其中第一覆层位于第一高k电介质层下方，第二覆层位于第二高k电介质层上。

7. 发明申请

US20050087790A1 HIGH-K DIELECTRIC STACK IN A MIM CAPACITOR AND METHOD FOR ITS FABRICATION 有权
标题翻译： MIM电容器中的高K介质堆叠及其制造方法
公开(公告)号：US20050087790A1
公开(公告)日：2005-04-28
申请号：US10692431
申请日：2003-10-22
申请人： Dieter Dornisch , David Howard , Abhijit Joshi
发明人： Dieter Dornisch , David Howard , Abhijit Joshi
IPC分类号： H01L21/02 , H01L21/316 , H01L21/318 , H01L29/00
CPC分类号： H01L21/022 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/0228 , H01L21/31612 , H01L21/31616 , H01L21/31637 , H01L21/31641 , H01L21/3185 , H01L28/40 , H01L28/56 , H01L28/75
摘要： According to one exemplary embodiment, a high-k dielectric stack situated between upper and lower electrodes of a MIM capacitor comprises a first high-k dielectric layer, where the first high-k dielectric layer has a first dielectric constant. The high-k dielectric stack further comprises an intermediate dielectric layer situated on the first high-k dielectric layer, where the intermediate dielectric layer has a second dielectric constant. According to this exemplary embodiment, the high-k dielectric stack further comprises a second high-k dielectric layer situated on the intermediate dielectric layer, where the second high-k dielectric layer has a third dielectric constant. The second dielectric constant can be lower than the first dielectric constant and the third dielectric constant. The high-k dielectric stack further comprises first and second cladding layers, where the first cladding layer is situated underneath the first high-k dielectric layer and the second cladding layer is situated on the second high-k dielectric layer.
摘要翻译：根据一个示例性实施例，位于MIM电容器的上电极和下电极之间的高k电介质堆叠包括第一高k电介质层，其中第一高k电介质层具有第一介电常数。高k电介质堆叠还包括位于第一高k电介质层上的中间电介质层，其中中间介电层具有第二介电常数。根据该示例性实施例，高k电介质堆叠还包括位于中间介电层上的第二高k电介质层，其中第二高k电介质层具有第三介电常数。第二介电常数可以低于第一介电常数和第三介电常数。高k电介质堆叠还包括第一和第二覆层，其中第一覆层位于第一高k电介质层下方，第二覆层位于第二高k电介质层上。

8. 发明授权

US06255192B1 Methods for barrier layer formation 有权
标题翻译：阻挡层形成方法
公开(公告)号：US06255192B1
公开(公告)日：2001-07-03
申请号：US09163135
申请日：1998-09-29
申请人： Dieter Dornisch
发明人： Dieter Dornisch
IPC分类号： H01L2176
CPC分类号： H01L21/76843 , H01L21/28568 , H01L21/3212 , H01L21/76877 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An improved microelectronic device and methods for forming the device are disclosed. The device includes a conductive feature formed on a semiconductor wafer by creating a trench within an insulating material, depositing barrier material substantially only within the trench, depositing conductive material on the wafer surface and within the trench, and removing the conductive material from the wafer surface. Alternately, the barrier material may be deposited onto the wafer surface and the trench and removed from the wafer surface prior to conductive material deposition.
摘要翻译：公开了一种改进的微电子器件和用于形成器件的方法。该器件包括通过在绝缘材料内形成沟槽而形成在半导体晶片上的导电特征，基本上仅在沟槽内沉积阻挡材料，在晶片表面上和沟槽内沉积导电材料，以及从晶片表面去除导电材料。或者，阻挡材料可以在导电材料沉积之前沉积到晶片表面和沟槽上并从晶片表面去除。

9. 发明申请

US20060110889A1 Method for fabricating a MIM capacitor having increased capacitance density and related structure 有权
标题翻译：具有增加的电容密度和相关结构的MIM电容器的制造方法
公开(公告)号：US20060110889A1
公开(公告)日：2006-05-25
申请号：US10997638
申请日：2004-11-23
申请人： Dieter Dornisch , Kenneth Ring , Tinghao Wang , David Howard , Guangming Li
发明人： Dieter Dornisch , Kenneth Ring , Tinghao Wang , David Howard , Guangming Li
IPC分类号： H01L21/20
CPC分类号： H01L28/40
摘要： According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um2.
摘要翻译：根据本发明的一个实施例，在半导体管芯中制造MIM电容器的方法包括沉积第一互连金属层的步骤。该方法还包括在第一互连层上沉积氮化硅层。氮化硅层在沉积过程中使用至少12.5的氨 - 硅烷比沉积。该方法还包括在氮化硅层上沉积MIM电容器金属层。该方法还包括蚀刻MIM电容器金属层以形成MIM电容器的上电极。根据该示例性实施例，该方法还包括蚀刻氮化硅层以形成MIM电容器电介质段并蚀刻第一互连金属层以形成MIM电容器的下电极。 MIM电容器具有至少2.0fF / um 2的电容密度。

10. 发明授权

US06709564B1 Integrated circuit plating using highly-complexed copper plating baths 有权
标题翻译：使用高度复合镀铜浴的集成电路电镀
公开(公告)号：US06709564B1
公开(公告)日：2004-03-23
申请号：US09410250
申请日：1999-09-30
申请人： D. Morgan Tench , John T. White , Dieter Dornisch , Maureen Brongo
发明人： D. Morgan Tench , John T. White , Dieter Dornisch , Maureen Brongo
IPC分类号： C25D338
CPC分类号： C25D3/38 , C25D7/123 , H01L21/2885 , H01L21/4846 , H01L21/76877
摘要： The acid copper sulfate solutions used for electroplating copper circuitry in trenches and vias in IC dielectric material in the Damascene process are replaced with a type of plating system based on the use of highly complexing anions (e.g., pyrophosphate, cyanide, sulfamate, etc.) to provide an inherently high overvoltage that effectively suppresses runaway copper deposition. Such systems, requiring only one easily-controlled organic additive species to provide outstanding leveling, are more efficacous for bottom-up filling of Damascene trenches and vias than acid copper sulfate baths, which require a minimum of two organic additive species. The highly complexed baths produce fine-grained copper deposits that are typically much harder than large-grained acid sulfate copper deposits, and which exhibit stable mechanical properties that do not change with time, thereby minimizing “dishing” and giving more consistent CMP results. The mechanical properties and texture of the fine-grained deposits are also much less substrate dependent, which minimizes the effects of variations and flaws in the barrier and seed layers. The resistivity of pyrophosphate and annealed acid sulfate copper deposits are approximately equivalent.
摘要翻译：用于电镀铜电路的酸性硫酸铜溶液用于在马赛克（Damascene）工艺中的IC电介质材料的沟槽和通孔中电镀铜电路，该电镀系统基于使用高度络合的阴离子（如焦磷酸盐，氰化物，氨基磺酸盐等）以提供有效抑制失控的铜沉积的固有的高过电压。与需要至少两种有机添加物种的酸性硫酸铜浴相比，仅需要一种容易控制的有机添加剂来提供优异的流平性的这种系统对于自底向上填充大马士革沟槽和通孔更有效。高度复杂的浴槽产生细粒度的铜沉积物，其通常比大粒度的硫酸硫酸铜沉积物更硬，并且其表现出不会随时间变化的稳定的机械性能，从而最小化“凹陷”并提供更一致的CMP结果。细颗粒沉积物的机械性能和质地也要小得多，从而使屏障和种子层的变化和缺陷的影响最小化。焦磷酸盐和退火的硫酸硫酸铜沉积物的电阻率大致相当。

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