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1. 发明授权

US06248618B1 Method of fabrication of dual gate oxides for CMOS devices 有权
标题翻译：制造CMOS器件双栅氧化物的方法
公开(公告)号：US06248618B1
公开(公告)日：2001-06-19
申请号：US09415246
申请日：1999-10-12
申请人： Shyue Fong Quek , Ting Cheong Ang , Puay Ing Ong , Sang Yee Loong
发明人： Shyue Fong Quek , Ting Cheong Ang , Puay Ing Ong , Sang Yee Loong
IPC分类号： H01L218238
CPC分类号： H01L21/823857 , Y10S438/981
摘要： A method of forming thick and thin gate oxides comprising the following steps. A silicon semiconductor substrate having first and second active areas separated by shallow isolation trench regions is provided. Oxide growth is selectively formed over the first active area by UV oxidation to form a first gate oxide layer having a first predetermined thickness. The first and second active areas are then simultaneously oxidized whereby the first predetermined thickness of the first gate oxide layer is increased to a second predetermined thickness and a second gate oxide layer having a predetermined thickness is formed in the second active area. The second predetermined thickness of the first oxide layer in the first active area is greater than the predetermined thickness of the second oxide layer in the second active area.
摘要翻译：一种形成厚薄的栅极氧化物的方法，包括以下步骤。提供具有由浅隔离沟槽区域隔开的第一和第二有源区的硅半导体衬底。通过UV氧化在第一有源区上选择性地形成氧化物生长，以形成具有第一预定厚度的第一栅氧化层。然后，第一和第二有源区域被同时氧化，由此第一栅极氧化物层的第一预定厚度增加到第二预定厚度，并且在第二有源区域中形成具有预定厚度的第二栅极氧化物层。第一有源区中的第一氧化物层的第二预定厚度大于第二有源区中第二氧化物层的预定厚度。

2. 发明授权

US06465296B1 Vertical source/drain contact semiconductor 有权
标题翻译：垂直源极/漏极接触半导体
公开(公告)号：US06465296B1
公开(公告)日：2002-10-15
申请号：US10167095
申请日：2002-06-10
申请人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
发明人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
IPC分类号： H01L218238
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76281 , H01L29/41733 , H01L29/458 , H01L29/66636 , H01L29/66825 , H01L29/78621
摘要： A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.
摘要翻译：提供了一种半导体器件及其制造方法，其中倾斜的掺杂剂注入之后是在与半导体栅极的侧面相邻的绝缘体上硅衬底中形成垂直沟槽。暴露在源极/漏极结中的第二掺杂剂注入之后是在衬底中形成半导体沟道的快速热退火。然后形成在半导体衬底中具有向内弯曲的横截面宽度的触头，其直接地或通过咸水接触区域垂直连接到暴露的源极/漏极接合点。

3. 发明授权

US06653674B2 Vertical source/drain contact semiconductor 失效
公开(公告)号：US06653674B2
公开(公告)日：2003-11-25
申请号：US10227124
申请日：2002-08-23
申请人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
发明人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
IPC分类号： H01L2976
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76281 , H01L27/1203 , H01L29/41733 , H01L29/458 , H01L29/66636 , H01L29/66825 , H01L29/78621
摘要： A semiconductor device is provided having angled dopant implantation and vertical trenches in the silicon on insulator substrate adjacent to the sides of a semiconductor gate. A second dopant implantation is in the exposed the source/drain junctions. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

4. 发明授权

US06284609B1 Method to fabricate a MOSFET using selective epitaxial growth to form lightly doped source/drain regions 有权
标题翻译：使用选择性外延生长制造MOSFET以形成轻掺杂源/漏区的方法
公开(公告)号：US06284609B1
公开(公告)日：2001-09-04
申请号：US09435437
申请日：1999-11-22
申请人： Ting Cheong Ang , Shyue Fong Quek , Puay Ing Ong , Sang Yee Loong
发明人： Ting Cheong Ang , Shyue Fong Quek , Puay Ing Ong , Sang Yee Loong
IPC分类号： H01L21336
CPC分类号： H01L29/66628 , H01L21/2257 , H01L21/28026 , H01L21/2807 , H01L29/4966 , H01L29/66545 , H01L29/7834
摘要： A new method of fabricating a sub-quarter micron MOSFET device is achieved. A semiconductor substrate is provided. Isolation regions are formed in this substrate. An oxide layer is provided overlying both the substrate and the isolation regions. The oxide layer is patterned and etched exposing two regions of the substrate. A selective epitaxial growth (SEG) is performed with in situ doping covering the two exposed substrate regions formed during the previous step. The doped SEG regions will form the source and drain contact regions of the MOSFET. The oxide layer region between the two doped SEG regions is then patterned and etched away exposing the substrate. This is followed by a gate oxide formation and either a polysilicon or metal gate deposition. Planarization is then performed on the surface to facilitate interconnection later in the process and to form the final gate structure. Thermal energy provided from processing steps or from a rapid thermal anneal (RTA) allows the doping atoms in the SEG regions to diffuse into the substrate thereby forming the active source/drain regions. This method allows precise control of the doping profile in the active source/drain region. An interlevel dielectric is then deposited over the entire surface. Contact holes are then etched in the interlevel dielectric and metalization patterned to allow interconnection to the completed MOSFET device.
摘要翻译：实现了制造二分之一微米MOSFET器件的新方法。提供半导体衬底。在该衬底中形成隔离区。提供覆盖衬底和隔离区域的氧化物层。图案化和蚀刻氧化层暴露衬底的两个区域。通过原位掺杂来执行选择性外延生长（SEG），覆盖在前一步骤期间形成的两个暴露的衬底区域。掺杂的SEG区域将形成MOSFET的源极和漏极接触区域。然后将两个掺杂的SEG区域之间的氧化物层区域图案化并蚀刻掉，暴露衬底。之后是栅极氧化物形成和多晶硅或金属栅极沉积。然后在表面上执行平面化，以便在该过程中稍后进行互连并形成最终的栅极结构。从加工步骤或快速热退火（RTA）提供的热能允许SEG区域中的掺杂原子扩散到衬底中，从而形成有源源极/漏极区域。该方法允许精确控制有源源极/漏极区域中的掺杂分布。然后在整个表面上沉积层间电介质。然后在层间电介质中蚀刻接触孔，并图案化金属化，以允许与完成的MOSFET器件互连。

5. 发明授权

US06261917B1 High-K MOM capacitor 有权
标题翻译：高K MOM电容
公开(公告)号：US06261917B1
公开(公告)日：2001-07-17
申请号：US09567420
申请日：2000-05-09
申请人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
发明人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/31683 , H01L28/75
摘要： A method for fabricating a metal-oxide-metal capacitor is described. A first insulating layer is provided overlying a semiconductor substrate. A barrier metal layer and a first metal layer are deposited over the insulating layer. A titanium layer is deposited overlying the first metal layer. The titanium layer is exposed to an oxidizing plasma while simultaneously a portion of the titanium layer where the metal-oxide-metal capacitor is to be formed is exposed to light whereby the portion of the titanium layer exposed to light reacts with the oxidizing plasma to form titanium oxide. Thereafter, the titanium layer is removed, leaving the titanium oxide layer where the metal-oxide-metal capacitor is to be formed. A second metal layer is deposited overlying the first metal layer and the titanium oxide layer. The second metal layer, titanium oxide layer, and first metal layer are patterned to form a metal-oxide-metal capacitor wherein the second metal layer forms an upper plate electrode, the titanium oxide layer forms a capacitor dielectric, and the first metal layer forms a bottom plate electrode of the MOM capacitor.
摘要翻译：对金属氧化物 - 金属电容器的制造方法进行说明。第一绝缘层设置在半导体衬底上。在绝缘层上沉积阻挡金属层和第一金属层。沉积钛层沉积在第一金属层上。将钛层暴露于氧化等离子体，同时将要形成金属 - 氧化物 - 金属电容器的钛层的一部分暴露于光，由此暴露于光的钛层的部分与氧化等离子体反应形成氧化钛。然后，除去钛层，留下要形成金属 - 氧化物 - 金属电容器的氧化钛层。沉积在第一金属层和氧化钛层上的第二金属层。对第二金属层，氧化钛层和第一金属层进行构图以形成金属氧化物 - 金属电容器，其中第二金属层形成上板电极，氧化钛层形成电容器电介质，第一金属层形成 MOM电容器的底板电极。

6. 发明授权

US06258677B1 Method of fabricating wedge isolation transistors 失效
标题翻译：楔形隔离晶体管的制造方法
公开(公告)号：US06258677B1
公开(公告)日：2001-07-10
申请号：US09409875
申请日：1999-10-01
申请人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
发明人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L21/76264 , H01L21/76278 , H01L21/76283 , H01L21/823878 , H01L29/41783 , H01L29/66545 , H01L29/66628 , H01L29/66651
摘要： A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.
摘要翻译：一种制造晶体管的方法，包括以下步骤。提供了具有限定其间的有源区域的具有间隔开的凸起的楔形介电隔离区域的硅半导体结构。在活性区域上生长外延硅以形成SEG区域。在SEG区域上形成一个虚拟门。凸起的外延硅层生长在与虚拟栅极相邻的SEG区域上。去除虚拟栅极，暴露凸起的外延硅层的内侧壁。在凸起的外延硅层的暴露的侧壁上形成侧壁间隔物。栅极氧化物层生长在SEG区域上并且在凸起的外延硅层的侧壁间隔物之间。在该结构上沉积一层多晶硅，并将其平坦化，以在SEG区域和凸出的外延硅层的侧壁间隔物之间形成栅极导体。去除侧壁间隔物。不需要HDP工艺沟槽填充来形成STI，并且不需要CMP工艺来平坦化STI。

7. 发明授权

US06611024B2 Method of forming PID protection diode for SOI wafer 有权
公开(公告)号：US06611024B2
公开(公告)日：2003-08-26
申请号：US09946981
申请日：2001-09-06
申请人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
发明人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
IPC分类号： H01L2701
CPC分类号： H01L21/84 , H01L27/1203
摘要： An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

8. 发明授权

US06406994B1 Triple-layered low dielectric constant dielectric dual damascene approach 有权
标题翻译：三层低介电常数电介质双镶嵌方法
公开(公告)号：US06406994B1
公开(公告)日：2002-06-18
申请号：US09726657
申请日：2000-11-30
申请人： Ting Cheong Ang , Shyue Fong Quek , Yee Chong Wong , Sang Yee Loong
发明人： Ting Cheong Ang , Shyue Fong Quek , Yee Chong Wong , Sang Yee Loong
IPC分类号： H01L2144
CPC分类号： B41M5/5254 , B41M5/508 , B41M5/5218 , B41M5/5272 , Y10T428/24802
摘要： A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material. If the first type is a low dielectric constant inorganic material, the second type will be a low dielectric constant organic material.
摘要翻译：描述了三层低介电常数材料双镶嵌金属化工艺。金属线被覆盖在半导体衬底上的绝缘层所覆盖。第一类型的第一介电层沉积在绝缘层上。第二类型的第二介电层沉积在第一介电层上。通孔图案被蚀刻到第二介电层中。此后，第一类型的第三电介质层沉积在图案化的第二介电层上。同时，沟槽图案被蚀刻到第三介电层中，并且通孔图案被蚀刻到第一介电层中，以在集成电路器件的制造中完成双镶嵌开口的形成。如果第一种类型是低介电常数有机材料，则第二种类型将是低介电常数无机材料。如果第一种类型是低介电常数无机材料，则第二类型将是低介电常数有机材料。

9. 发明授权

US06787422B2 Method of body contact for SOI mosfet 有权
标题翻译： SOI mosfet的身体接触方法
公开(公告)号：US06787422B2
公开(公告)日：2004-09-07
申请号：US09755572
申请日：2001-01-08
申请人： Ting Cheong Ang , Sang Yee Loong , Shyue Fong Quek , Jun Song
发明人： Ting Cheong Ang , Sang Yee Loong , Shyue Fong Quek , Jun Song
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.
摘要翻译：描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。第一和第二沟槽填充有绝缘层。栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。沉积覆盖栅电极的层间电介质层。第一触点通过层间介质层开放到下面的源极和漏极区域。在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

10. 发明授权

US06495399B1 Method of vacuum packaging a semiconductor device assembly 失效
标题翻译：真空包装半导体器件组件的方法
公开(公告)号：US06495399B1
公开(公告)日：2002-12-17
申请号：US09431238
申请日：1999-11-01
申请人： Shyue-Fong Quek , Ting Cheong Ang , Duay Ing Ong , Sang Yee Loong
发明人： Shyue-Fong Quek , Ting Cheong Ang , Duay Ing Ong , Sang Yee Loong
IPC分类号： H01L2150
CPC分类号： H01L23/3107 , H01L23/5221 , H01L23/5222 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2924/1433 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.
摘要翻译：一种半导体芯片器件封装，包括形成在半导体衬底上的具有半导体器件的半导体衬底。至少一个电介质层在半导体衬底之上。至少一层互连在半导体器件之上，并且在至少一个相应的电介质层内，其中至少一部分互连由其中具有真空或空气的空隙分开。钝化层位于至少一层互连层的最上面。其中半导体芯片器件被真空密封在半导体芯片器件封装内。

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