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1. 发明授权

US06883152B2 Voltage island chip implementation 失效
标题翻译：电压岛芯片实现
公开(公告)号：US06883152B2
公开(公告)日：2005-04-19
申请号：US10867914
申请日：2004-06-15
申请人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
发明人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.
摘要翻译：用于设计集成电路芯片的方法和结构提供芯片设计，并且根据电压要求的相似性和元件的功率状态的时序来分配芯片设计的元件以产生电压岛。本发明输出包括每个电压岛的功率和定时信息的电压岛规格表; 并自动，无需用户干预，就可以合成电压岛的供电网络。

2. 发明授权

US06820240B2 Voltage island chip implementation 有权
标题翻译：电压岛芯片实现
公开(公告)号：US06820240B2
公开(公告)日：2004-11-16
申请号：US10065201
申请日：2002-09-25
申请人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
发明人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.
摘要翻译：用于设计集成电路芯片的方法和结构提供芯片设计，并且根据电压要求的相似性和元件的功率状态的时序来分配芯片设计的元件以产生电压岛。本发明输出包括每个电压岛的功率和定时信息的电压岛规格表; 并自动，无需用户干预，就可以合成电压岛的供电网络。

3. 发明授权

US06779163B2 Voltage island design planning 有权
公开(公告)号：US06779163B2
公开(公告)日：2004-08-17
申请号：US10065202
申请日：2002-09-25
申请人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
发明人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5068
摘要： A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands, creates a floorplan of the voltage islands, assesses the floorplan, repeats the partitioning and the creating of the floorplan depending upon a result of the assessing process, and outputs a voltage island specification list.

4. 发明授权

US07096436B2 Macro design techniques to accommodate chip level wiring and circuit placement across the macro 有权
公开(公告)号：US07096436B2
公开(公告)日：2006-08-22
申请号：US10946552
申请日：2004-09-21
申请人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
发明人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , Y10S707/99931
摘要： Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.

5. 发明授权

US06883155B2 Macro design techniques to accommodate chip level wiring and circuit placement across the macro 失效
公开(公告)号：US06883155B2
公开(公告)日：2005-04-19
申请号：US10403626
申请日：2003-03-31
申请人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
发明人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/5068 , Y10S707/99931
摘要： Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.

6. 发明授权

US06543040B1 Macro design techniques to accommodate chip level wiring and circuit placement across the macro 有权
标题翻译：宏观设计技术，以适应芯片级布线和电路布局
公开(公告)号：US06543040B1
公开(公告)日：2003-04-01
申请号：US09526198
申请日：2000-03-15
申请人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
发明人： Thomas R. Bednar , Paul E. Dunn , Scott W. Gould , Jeannie H. Panner , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , Y10S707/99931
摘要： Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.
摘要翻译：公开了宏观设计技术，以便于跨宏观的后续布线。重新布置宏中的空白区域以适应布线。重新布置可以采取将空白区域的物理重新布置成从宏的一侧延伸到另一侧的路由轨道的形式; 使用例如宏功率总线和/或宏布线进行屏蔽; 路由功率总线到重新排列的空格; 和/或插入具有可接线的引脚的有源电路。在优选实施例中，在后续阶段的设计期间，将有源电路放置在重排的宏空白中。空白的重新排列有助于宏观上的布线，使得可以保持后续级布线的压摆率和路径延迟要求，而不会过度缓冲或重新布线。

7. 发明授权

US07961932B2 Method and apparatus for manufacturing diamond shaped chips 有权
标题翻译：用于制造菱形芯片的方法和装置
公开(公告)号：US07961932B2
公开(公告)日：2011-06-14
申请号：US11865728
申请日：2007-10-01
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

8. 发明授权

US07289659B2 Method and apparatus for manufacturing diamond shaped chips 有权
标题翻译：用于制造菱形芯片的方法和装置
公开(公告)号：US07289659B2
公开(公告)日：2007-10-30
申请号：US10250295
申请日：2003-06-20
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

9. 发明授权

US06490708B2 Method of integrated circuit design by selection of noise tolerant gates 失效
公开(公告)号：US06490708B2
公开(公告)日：2002-12-03
申请号：US09812211
申请日：2001-03-19
申请人： John M. Cohn , Scott W. Gould , Peter A. Habitz , Jose L. P. Neves , William F. Smith , Larry Wissel , Paul S. Zuchowski
发明人： John M. Cohn , Scott W. Gould , Peter A. Habitz , Jose L. P. Neves , William F. Smith , Larry Wissel , Paul S. Zuchowski
IPC分类号： G06E1750
CPC分类号： G06F17/505
摘要： A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and ordering the cells in each group from one extreme to the other extreme value of a featured parameter for which the integrated circuit is to be tested. Each one of the cells in the library have a known value of another parameter so that the substitution of a library cell for an original cell or another library cell does not affect the overall integrated circuit value for that known parameter. A substitution can thus be made with the knowledge that additional problems involving the known parameter are not being created. If a test of the integrated circuit discovers a problem in a particular cell's performance with regard to the featured parameter the appropriate library group is accessed and the failing cell is replaced with the first unused cell in the group. The process is repeated until the integrated circuit passes a performance test.

10. 发明授权

US06825711B2 Power reduction by stage in integrated circuit 有权
标题翻译：集成电路中的功耗降低
公开(公告)号：US06825711B2
公开(公告)日：2004-11-30
申请号：US10249684
申请日：2003-04-30
申请人： John M. Cohn , Kenneth J. Goodnow , Scott W. Gould , Douglas W. Stout , Sebastian T. Ventrone
发明人： John M. Cohn , Kenneth J. Goodnow , Scott W. Gould , Douglas W. Stout , Sebastian T. Ventrone
IPC分类号： G05F110
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.
摘要翻译：一种集成电路，方法和系统，提供更精细的粒度动态电压控制，无需性能损失。本发明提供了用于在特定周期中动态地改变关键路径上的至少一个级的电压电平的装置。以这种方式，可以为给定期望的阶段提供最佳电压。

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