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1. 发明授权

US06883152B2 Voltage island chip implementation 失效
标题翻译：电压岛芯片实现
公开(公告)号：US06883152B2
公开(公告)日：2005-04-19
申请号：US10867914
申请日：2004-06-15
申请人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
发明人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.
摘要翻译：用于设计集成电路芯片的方法和结构提供芯片设计，并且根据电压要求的相似性和元件的功率状态的时序来分配芯片设计的元件以产生电压岛。本发明输出包括每个电压岛的功率和定时信息的电压岛规格表; 并自动，无需用户干预，就可以合成电压岛的供电网络。

2. 发明授权

US06779163B2 Voltage island design planning 有权
公开(公告)号：US06779163B2
公开(公告)日：2004-08-17
申请号：US10065202
申请日：2002-09-25
申请人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
发明人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5068
摘要： A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands, creates a floorplan of the voltage islands, assesses the floorplan, repeats the partitioning and the creating of the floorplan depending upon a result of the assessing process, and outputs a voltage island specification list.

3. 发明授权

US06820240B2 Voltage island chip implementation 有权
标题翻译：电压岛芯片实现
公开(公告)号：US06820240B2
公开(公告)日：2004-11-16
申请号：US10065201
申请日：2002-09-25
申请人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
发明人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.
摘要翻译：用于设计集成电路芯片的方法和结构提供芯片设计，并且根据电压要求的相似性和元件的功率状态的时序来分配芯片设计的元件以产生电压岛。本发明输出包括每个电压岛的功率和定时信息的电压岛规格表; 并自动，无需用户干预，就可以合成电压岛的供电网络。

4. 发明授权

US08504971B2 Method and device for selectively adding timing margin in an integrated circuit 有权
标题翻译：用于在集成电路中选择性地添加定时裕度的方法和装置
公开(公告)号：US08504971B2
公开(公告)日：2013-08-06
申请号：US13355099
申请日：2012-01-20
申请人： David E. Lackey , Chandramouili Visweswariah , Paul S. Zuchowski
发明人： David E. Lackey , Chandramouili Visweswariah , Paul S. Zuchowski
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031 , G01R31/318307 , G01R31/318364
摘要： A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.
摘要翻译：一种方法，系统和集成电路，包括选择性地添加定时裕度。用于集成统计时序和自动测试模式生成（ATPG）以在集成电路中选择性地添加时序裕度的方法包括在芯片设计时识别在制造测试期间“以速度”无法被鲁棒测试的路径，运行统计计时，计算要应用于路径的余量，更新要应用于路径的余量的设计规范，以及基于更新的设计规范优化芯片逻辑。

5. 发明授权

US08122409B2 Method and device for selectively adding timing margin in an integrated circuit 有权
标题翻译：用于在集成电路中选择性地添加定时裕度的方法和装置
公开(公告)号：US08122409B2
公开(公告)日：2012-02-21
申请号：US11869306
申请日：2007-10-09
申请人： David E. Lackey , Chandramouli Visweswariah , Paul S. Zuchowski
发明人： David E. Lackey , Chandramouli Visweswariah , Paul S. Zuchowski
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G01R31/318307 , G01R31/318364
摘要： A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.
摘要翻译：一种方法，系统和集成电路，包括选择性地添加定时裕度。用于集成统计时序和自动测试模式生成（ATPG）以在集成电路中选择性地添加时序裕度的方法包括在芯片设计时识别在制造测试期间“以速度”无法被鲁棒测试的路径，运行统计计时，计算要应用于路径的余量，更新要应用于路径的余量的设计规范，以及基于更新的设计规范优化芯片逻辑。

6. 发明授权

US08589843B2 Method and device for selectively adding timing margin in an integrated circuit 有权
公开(公告)号：US08589843B2
公开(公告)日：2013-11-19
申请号：US13355065
申请日：2012-01-20
申请人： David E. Lackey , Chandramouili Visweswariah , Paul S. Zuchowski
发明人： David E. Lackey , Chandramouili Visweswariah , Paul S. Zuchowski
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G01R31/318307 , G01R31/318364
摘要： A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.

7. 发明授权

US08490045B2 Method and device for selectively adding timing margin in an integrated circuit 有权
公开(公告)号：US08490045B2
公开(公告)日：2013-07-16
申请号：US13354715
申请日：2012-01-20
申请人： David E. Lackey , Chandramouili Visweswariah , Paul S. Zuchowski
发明人： David E. Lackey , Chandramouili Visweswariah , Paul S. Zuchowski
IPC分类号： G06F9/455 , G06F17/50 , G06F11/22
CPC分类号： G06F17/5031 , G01R31/318307 , G01R31/318364
摘要： A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.

8. 发明申请

US20090094565A1 METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT 有权
标题翻译：用于在集成电路中选择性地添加时序的方法和设备
公开(公告)号：US20090094565A1
公开(公告)日：2009-04-09
申请号：US11869306
申请日：2007-10-09
申请人： David E. Lackey , Chandramouli Visweswariah , Paul S. Zuchowski
发明人： David E. Lackey , Chandramouli Visweswariah , Paul S. Zuchowski
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G01R31/318307 , G01R31/318364
摘要： A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.
摘要翻译：一种方法，系统和集成电路，包括选择性地添加定时裕度。用于集成统计时序和自动测试模式生成（ATPG）以在集成电路中选择性地添加时序裕度的方法包括在芯片设计时识别在制造测试期间“以速度”无法被鲁棒测试的路径，运行统计计时，计算要应用于路径的余量，更新要应用于路径的余量的设计规范，以及基于更新的设计规范优化芯片逻辑。

9. 发明授权

US07996739B2 Avoiding race conditions at clock domain crossings in an edge based scan design 有权
标题翻译：在边缘扫描设计中避免时钟域交叉处的竞争条件
公开(公告)号：US07996739B2
公开(公告)日：2011-08-09
申请号：US12557623
申请日：2009-09-11
申请人： David E. Lackey
发明人： David E. Lackey
IPC分类号： G01R31/28
CPC分类号： G01R31/318594
摘要： A structure, system, and method block clock inputs to clock domains (using a computer). While the clock domain inputs are blocked, the structure, system, and method perform a first timing test only of signals that are transmitted within the clock domains (using the computer) by only observing latches that receive signals from sources within the clock domains. The structure, system, and method also unblock the clock inputs to the clock domains (using the computer). While the clock domain inputs are unblocked, the structure, system, and method perform a second timing test only of signals that are transmitted between the clock domains by only observing latches that receive signals from other clock domains.
摘要翻译：一种结构，系统和方法将时钟域的时钟输入（使用计算机）。当时钟域输入被阻塞时，结构，系统和方法仅通过仅观察从时钟域内的源接收信号的锁存器来执行在时钟域（使用计算机）内发送的信号的第一定时测试。结构，系统和方法还可以解除对时钟域的时钟输入（使用计算机）。当时钟域输入被解除阻塞时，结构，系统和方法仅通过仅观察从其它时钟域接收信号的锁存器来执行在时钟域之间传输的信号的第二定时测试。

10. 发明授权

US07937632B2 Design structure and apparatus for a robust embedded interface 有权
标题翻译：用于强大的嵌入式接口的设计结构和设备
公开(公告)号：US07937632B2
公开(公告)日：2011-05-03
申请号：US12144703
申请日：2008-06-24
申请人： Steven M. Eustis , Kevin W. Gorman , David E. Lackey , Michael R. Ouellette
发明人： Steven M. Eustis , Kevin W. Gorman , David E. Lackey , Michael R. Ouellette
IPC分类号： G11C29/14 , G11C29/50
CPC分类号： G11C29/36 , G11C29/1201 , G11C29/48 , G11C2029/0401
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。该设计结构包括耦合到数据处理单元输入的输入寄存器和测试操作模式和功能操作模式。在测试模式操作中，寄存器以时钟模式操作，使得在测试操作模式期间，寄存器响应于时钟信号将数据传播到数据处理单元。在功能操作模式中，寄存器以数据刷新模式运行，使得寄存器响应于数据将数据传播到数据处理单元。功能模式由刷新使能信号使能，测试模式通过刷新使能信号的相反状态使能。

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