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1. 发明授权

US08902956B2 On-package input/output clustered interface having full and half-duplex modes 有权
标题翻译：集成式输入/输出集群接口，具有全双工和半双工模式
公开(公告)号：US08902956B2
公开(公告)日：2014-12-02
申请号：US13995015
申请日：2011-12-22
申请人： Thomas P. Thomas , Stanley S. Kulick , Randy B. Osborne
发明人： Thomas P. Thomas , Stanley S. Kulick , Randy B. Osborne
IPC分类号： H04B1/38 , H04B3/02 , G06F15/78 , G06F13/40 , H03K19/0175
CPC分类号： G06F13/4068 , G06F13/4086 , G06F15/7825 , H03K19/017545 , H04B3/02 , H04B14/023
摘要： An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.
摘要翻译：一种用于控制片上网络流量的装置和系统。该装置的实施例包括在第一芯片上用于与第二芯片耦合的单端传输电路和单端接收电路，所述传输电路具有阻抗匹配和缺少均衡，接收电路缺少均衡，传输电路和接收电路具有静态可配置的特征并且被组织成簇，其中所述簇具有用于不同配置的可配置特征的相同的物理层电路设计，所述可配置特征包括半双工模式和全双工模式，其中第一芯片和第二芯片是在相同的封装上，并且其中用于将第一芯片与第二芯片耦合的多条导线匹配。

2. 发明授权

US09143120B2 Mechanisms for clock gating 有权
标题翻译：时钟门控机制
公开(公告)号：US09143120B2
公开(公告)日：2015-09-22
申请号：US13997840
申请日：2011-12-22
申请人： Randy B. Osborne , Stanley S. Kulick , Erin Francom , Thomas P. Thomas
发明人： Randy B. Osborne , Stanley S. Kulick , Erin Francom , Thomas P. Thomas
IPC分类号： G06F1/04 , H03K5/15 , G06F1/06 , G06F1/10 , G06F1/32
CPC分类号： H03K5/15 , G06F1/06 , G06F1/10 , G06F1/32
摘要： Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package. Gating elements within the clock signal distribution network disable the clock signal to one or more portions of the clock signal distribution network. A digital locked loop (DLL) maintains settings without tracking when the clock signal is disabled.
摘要翻译：时钟门控机制时钟发生电路通过集成电路封装内的时钟信号分配网络提供时钟信号。时钟信号分配网络内的选通元件将时钟信号禁止到时钟信号分配网络的一个或多个部分。数字锁定环（DLL）在禁止时钟信号时保持设置而不进行跟踪。

3. 发明申请

US20140009195A1 MECHANISMS FOR CLOCK GATING 有权
标题翻译：时钟效应机制
公开(公告)号：US20140009195A1
公开(公告)日：2014-01-09
申请号：US13997840
申请日：2011-12-22
申请人： Randy B. Osborne , Stanley S. Kulick , Erin Francom , Thomas P. Thomas
发明人： Randy B. Osborne , Stanley S. Kulick , Erin Francom , Thomas P. Thomas
IPC分类号： H03K5/15
CPC分类号： H03K5/15 , G06F1/06 , G06F1/10 , G06F1/32
摘要： Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package. Gating elements within the clock signal distribution network disable the clock signal to one or more portions of the clock signal distribution network. A digital locked loop (DLL) maintains settings without tracking when the clock signal is disabled.
摘要翻译：时钟门控机制时钟发生电路通过集成电路封装内的时钟信号分配网络提供时钟信号。时钟信号分配网络内的选通元件将时钟信号禁止到时钟信号分配网络的一个或多个部分。数字锁定环（DLL）在禁止时钟信号时保持设置而不进行跟踪。

4. 发明申请

US20130322556A1 ON-PACKAGE INPUT/OUTPUT CLUSTERED INTERFACE HAVING FULL AND HALF-DUPLEX MODES 有权
标题翻译：具有全双工模式的封装输入/输出集群接口
公开(公告)号：US20130322556A1
公开(公告)日：2013-12-05
申请号：US13995015
申请日：2011-12-22
申请人： Thomas P. Thomas , Stanley S. Kulick , Randy B. Osborne
发明人： Thomas P. Thomas , Stanley S. Kulick , Randy B. Osborne
IPC分类号： G06F13/40 , H04B3/02
CPC分类号： G06F13/4068 , G06F13/4086 , G06F15/7825 , H03K19/017545 , H04B3/02 , H04B14/023
摘要： An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.
摘要翻译：一种用于控制片上网络流量的装置和系统。该装置的实施例包括在第一芯片上用于与第二芯片耦合的单端传输电路和单端接收电路，所述传输电路具有阻抗匹配和缺少均衡，接收电路缺少均衡，传输电路和接收电路具有静态可配置特征并且被组织成群集，其中所述簇具有用于不同配置的可配置特征的相同物理层电路设计，所述可配置特征包括半双工模式和全双工模式，其中所述第一芯片和所述第二芯片是在相同的封装上，并且其中用于将第一芯片与第二芯片耦合的多条导线匹配。

5. 发明授权

US09535865B2 Interconnection of multiple chips in a package 有权
标题翻译：封装中多个芯片的互连
公开(公告)号：US09535865B2
公开(公告)日：2017-01-03
申请号：US13996107
申请日：2011-12-22
申请人： Thomas P. Thomas , Randy B. Osborne , Rajesh Kumar
发明人： Thomas P. Thomas , Randy B. Osborne , Rajesh Kumar
IPC分类号： G06F13/00 , G06F13/364 , G06F13/14 , G06F13/40 , G06F13/42 , G06F3/0488 , G06F13/16
CPC分类号： G06F13/364 , G06F3/0488 , G06F13/14 , G06F13/16 , G06F13/4068 , G06F13/4273 , Y02D10/14 , Y02D10/151
摘要： An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched.
摘要翻译：一个接口第一组单端发射器电路驻留在具有主器件的第一管芯上。第一组单端接收器电路驻留在第二管芯上。接收器电路没有终端，没有均衡。第二管芯具有响应于第一管芯的主器件的从器件。导电线连接第一组发射器电路和第一组接收器电路。导线的长度相匹配。

6. 发明申请

US20140201405A1 INTERCONNECTION OF MULTIPLE CHIPS IN A PACKAGE UTILIZING ON-PACKAGE INPUT/OUTPUT INTERFACES 有权
标题翻译：使用封装输入/输出接口的封装中的多个插座的互连
公开(公告)号：US20140201405A1
公开(公告)日：2014-07-17
申请号：US13996107
申请日：2011-12-22
申请人： Thomas P. Thomas , Randy B. Osborne , Rajesh Kumar
发明人： Thomas P. Thomas , Randy B. Osborne , Rajesh Kumar
IPC分类号： G06F13/364 , G06F13/16 , G06F3/0488
CPC分类号： G06F13/364 , G06F3/0488 , G06F13/14 , G06F13/16 , G06F13/4068 , G06F13/4273 , Y02D10/14 , Y02D10/151
摘要： An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched.
摘要翻译：一个接口第一组单端发射器电路驻留在具有主器件的第一管芯上。第一组单端接收器电路驻留在第二管芯上。接收器电路没有终端，没有均衡。第二管芯具有响应于第一管芯的主器件的从器件。导电线连接第一组发射器电路和第一组接收器电路。导线的长度相匹配。

7. 发明申请

US20140204490A1 DISTRIBUTED ELECTROSTATIC DISCHARGE PROTECTION FOR AN ON-PACKAGE INPUT/OUTPUT ARCHITECTURE 有权
标题翻译：分布式输入/输出结构的分布式静电放电保护
公开(公告)号：US20140204490A1
公开(公告)日：2014-07-24
申请号：US13995111
申请日：2011-12-22
申请人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas
发明人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas
IPC分类号： H02H9/04 , G06F1/16
CPC分类号： H02H9/046 , G06F1/16 , G06F1/1613 , H01L27/0255 , H03K19/00361
摘要： An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
摘要翻译：一个封装接口。第一组第一组单端发射机电路。第二组芯片上的第一组单端接收器电路。接收器电路具有包括反相器和电阻反馈元件的终端电路。多条导线耦合第一组发射机电路和第一组接收机电路。多条导线的长度相匹配。

8. 发明申请

US20140089549A1 NON-LINEAR TERMINATION FOR AN ON-PACKAGE INPUT/OUTPUT ARCHITECTURE 有权
标题翻译：用于封装输入/输出结构的非线性终止
公开(公告)号：US20140089549A1
公开(公告)日：2014-03-27
申请号：US13995110
申请日：2011-12-22
申请人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas , Rajesh Kumar
发明人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas , Rajesh Kumar
IPC分类号： G06F13/36
CPC分类号： G06F13/4086 , G06F13/14 , G06F13/36 , Y02D10/14 , Y02D10/151
摘要： An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched.
摘要翻译：一个封装接口。第一组第一组单端发射机电路。第二组芯片上的第一组单端接收器电路。接收器电路具有包括反相器和电阻反馈元件的终端电路。多条导线耦合第一组发射机电路和第一组接收机电路。多个导线的长度匹配。

9. 发明授权

US07049704B2 Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board 失效
标题翻译：整合光学和电气设备并耦合到板上波导的倒装芯片封装
公开(公告)号：US07049704B2
公开(公告)日：2006-05-23
申请号：US10840017
申请日：2004-05-06
申请人： Kishore K. Chakravorty , Johanna Swan , Brandon C. Barnett , Joseph F. Ahadian , Thomas P. Thomas , Ian Young
发明人： Kishore K. Chakravorty , Johanna Swan , Brandon C. Barnett , Joseph F. Ahadian , Thomas P. Thomas , Ian Young
IPC分类号： H01L29/40
CPC分类号： G02B6/42 , G02B6/4206 , G02B6/4212 , G02B6/4214 , G02B6/4231 , G02B6/43 , H05K1/0274 , H05K3/3436 , H05K2201/10121 , H05K2201/10734
摘要： A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has an optical waveguide structure in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens directly attached to it to facilitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a Ball Grid Array (BGA) package. The BGA package is bonded to the PCB using solder reflow technology.
摘要翻译：允许一个或多个集成电路和印刷电路板（PCB）之间的电和光耦合的封装除了电连接之外还具有光波导结构。使用焊料凸块技术将光学有源器件直接贴合到集成电路上。光学器件具有直接连接到其上的透镜，以便于光耦合到光波导。集成电路倒装芯片结合到球栅阵列（BGA）封装。使用焊锡回流技术将BGA封装结合到PCB。

10. 发明授权

US06741102B1 Phase frequency detector 失效
标题翻译：相频检测器
公开(公告)号：US06741102B1
公开(公告)日：2004-05-25
申请号：US09300757
申请日：1999-04-26
申请人： Thomas P. Thomas
发明人： Thomas P. Thomas
IPC分类号： H03L7089
CPC分类号： H03L7/089 , H03D13/004 , H03L7/183
摘要： Briefly, in accordance with one embodiment, an integrated circuit includes a phase-frequency detector (PFD) including two clock input ports, an up signal port and a down signal port. The PFD includes digital circuitry including transistors coupled in a configuration to adjust an amount of overlap of an up output signal pulse and a down output signal pulse based, at least in part, upon the magnitude of an amount of phase delay between two respective clock signal pulses applied to the two input ports. Of course, additional embodiments are also disclosed.
摘要翻译：简而言之，根据一个实施例，集成电路包括包括两个时钟输入端口，上行信号端口和下行信号端口的相位频率检测器（PFD）。 PFD包括数字电路，其包括以配置来耦合的晶体管，以至少部分地基于两个相应时钟信号之间的相位延迟量的大小来调整上输出信号脉冲和下输出信号脉冲的重叠量施加到两个输入端口的脉冲。当然，还公开了另外的实施例。

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