专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070111547A1 Method for producing a semiconductor structure 审中-公开
标题翻译：半导体结构的制造方法
公开(公告)号：US20070111547A1
公开(公告)日：2007-05-17
申请号：US11582656
申请日：2006-10-18
申请人： Thomas Hecht , Stefan Jakschik , Christian Kapteyn
发明人： Thomas Hecht , Stefan Jakschik , Christian Kapteyn
IPC分类号： H01L21/31
CPC分类号： H01L21/31111 , H01L21/28202 , H01L21/823857 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66181 , H01L29/78
摘要： In a method for producing a semiconductor structure a substrate is provided, a dielectric layer comprising at least one metal oxide is formed on the substrate, and a nitrided layer is formed from the dielectric layer. The nitrided layer comprises either at least one metal nitride corresponding to the metal oxide or a metal oxynitride. The nitrided layer is removed selectively with respect to the dielectric layer in a predetermined etching medium.
摘要翻译：在制造半导体结构体的方法中，提供了基板，在基板上形成包含至少一种金属氧化物的电介质层，并且从电介质层形成氮化层。氮化层包括至少一种对应于金属氧化物的金属氮化物或金属氮氧化物。在预定的蚀刻介质中相对于电介质层选择性地去除氮化层。

2. 发明授权

US07176514B2 Method and configuration for reinforcement of a dielectric layer at defects by self-aligning and self-limiting electrochemical conversion of a substrate material 有权
标题翻译：通过衬底材料的自对准和自限制电化学转换来加强缺陷处的介电层的方法和结构
公开(公告)号：US07176514B2
公开(公告)日：2007-02-13
申请号：US10413812
申请日：2003-04-15
申请人： Thomas Hecht , Albert Birner , Harald Seidl , Uwe Schröder , Stefan Jakschik , Martin Gutsche
发明人： Thomas Hecht , Albert Birner , Harald Seidl , Uwe Schröder , Stefan Jakschik , Martin Gutsche
IPC分类号： H01L27/108 , H01L21/76
CPC分类号： H01L21/02238 , C25D11/02 , C25D11/32 , H01L21/02258 , H01L21/31675 , H01L21/31687 , H01L27/1085
摘要： A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.
摘要翻译：用于在由导电基板材料制成的基板上制造介电层的方法包括至少通过导电基板材料的自对准和自限制电化学转换为不导电的方式减少流过电介质层的缺陷的漏电流衬底跟随材料在与缺陷相邻的衬底的部分中。还提供了包括具有缺陷的电介质层，由导电基板材料制成的基板以及由与该缺陷相邻的部分中的非导电性基板追随材料制成的加强区域的结构。

3. 发明申请

US20060234463A1 Method for fabricating an electrical component 有权
标题翻译：电气部件的制造方法
公开(公告)号：US20060234463A1
公开(公告)日：2006-10-19
申请号：US11399811
申请日：2006-04-07
申请人： Alejandro Avellan , Thomas Hecht , Stefan Jakschik , Uwe Schroeder
发明人： Alejandro Avellan , Thomas Hecht , Stefan Jakschik , Uwe Schroeder
IPC分类号： H01L21/20 , H01L21/8242 , H01L21/31 , H01L21/469
CPC分类号： H01L28/65 , H01L27/1087 , H01L29/66181
摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.
摘要翻译：制造诸如DRAM半导体存储器或场效应晶体管的电气部件。制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。

4. 发明申请

US20080197428A1 Gate Electrode Structure, MOS Field Effect Transistors and Methods of Manufacturing the Same 有权
标题翻译：栅电极结构，MOS场效应晶体管及其制造方法
公开(公告)号：US20080197428A1
公开(公告)日：2008-08-21
申请号：US11675460
申请日：2007-02-15
申请人： Stefan Jakschik , Thomas Hecht
发明人： Stefan Jakschik , Thomas Hecht
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L21/28026 , H01L21/28061 , H01L21/823842 , H01L29/42372 , H01L29/4925 , H01L29/517 , H01L29/7833 , H01L29/7845
摘要： A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is amplified. Tensile or compressive strain may be induced in a crystalline substrate. Electron or hole mobility may be increased and on-resistance characteristics of a MOS field effect transistor may be improved.
摘要翻译：栅电极结构包括至少一个双层，其中每个双层包括镀膜和应力放大膜。镀膜包括多晶材料。应力放大器膜确定多晶材料的结晶结果，其中通过镀层诱导的机械应力被放大。可能在结晶底物中诱导拉伸或压缩应变。可以增加电子或空穴迁移率，并可提高MOS场效应晶体管的导通电阻特性。

5. 发明授权

US07268037B2 Method for fabricating microchips using metal oxide masks 有权
标题翻译：使用金属氧化物掩模制造微芯片的方法
公开(公告)号：US07268037B2
公开(公告)日：2007-09-11
申请号：US11040091
申请日：2005-01-24
申请人： Stefan Jakschik , Thomas Hecht , Uwe Schröder , Matthias Goldbach
发明人： Stefan Jakschik , Thomas Hecht , Uwe Schröder , Matthias Goldbach
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L21/31111 , H01L21/3141 , H01L21/31616 , H01L29/66181
摘要： A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.
摘要翻译：用于修改半导体部分的方法包括覆盖这些部分以保持不掺杂金属氧化物，例如氧化铝。然后，在未被氧化铝覆盖的那些部分中，例如从气相掺杂半导体。最后，再次选择性地除去氧化铝，例如使用热磷酸。由硅，氧化硅或氮化硅形成的半导体表面的部分保留在晶片上。

6. 发明授权

US07842977B2 Gate electrode structure, MOS field effect transistors and methods of manufacturing the same 有权
标题翻译：栅电极结构，MOS场效应晶体管及其制造方法相同
公开(公告)号：US07842977B2
公开(公告)日：2010-11-30
申请号：US11675460
申请日：2007-02-15
申请人： Stefan Jakschik , Thomas Hecht
发明人： Stefan Jakschik , Thomas Hecht
IPC分类号： H01L29/78
CPC分类号： H01L21/28026 , H01L21/28061 , H01L21/823842 , H01L29/42372 , H01L29/4925 , H01L29/517 , H01L29/7833 , H01L29/7845
摘要： A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is amplified. Tensile or compressive strain may be induced in a crystalline substrate. Electron or hole mobility may be increased and on-resistance characteristics of a MOS field effect transistor may be improved.
摘要翻译：栅电极结构包括至少一个双层，其中每个双层包括镀膜和应力放大膜。镀膜包括多晶材料。应力放大器膜确定多晶材料的结晶结果，其中通过镀层诱导的机械应力被放大。可能在结晶底物中诱导拉伸或压缩应变。可以增加电子或空穴迁移率，并可提高MOS场效应晶体管的导通电阻特性。

7. 发明申请

US20060202250A1 Storage capacitor, array of storage capacitors and memory cell array 审中-公开
标题翻译：存储电容器，存储电容器阵列和存储单元阵列
公开(公告)号：US20060202250A1
公开(公告)日：2006-09-14
申请号：US11076021
申请日：2005-03-10
申请人： Thomas Hecht , Uwe Schroeder , Till Schloesser , Stefan Jakschik , Alejandro Avellan
发明人： Thomas Hecht , Uwe Schroeder , Till Schloesser , Stefan Jakschik , Alejandro Avellan
IPC分类号： H01L29/94
CPC分类号： H01L27/10852 , H01L27/0207 , H01L28/82
摘要： A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the counter electrode being isolated from the storage electrode by the dielectric layer, wherein the storage electrode is formed as a body which is delimited by at least one curved surface having a center of curvature outside the body in a plane parallel to the substrate surface. According to another configuration, the storage electrode is formed as a body which is delimited by at least one set having two contiguous planes, the two planes extending perpendicularly with respect to the substrate surface, a point of intersection of normals of the two planes lying outside the body.
摘要翻译：适用于DRAM单元的存储电容器至少部分地形成在衬底表面之上，并且包括：至少部分地形成在衬底表面上方的存储电极，与存储电极相邻形成的电介质层和形成的对电极所述对置电极通过所述电介质层与所述存储电极隔离，其中所述存储电极形成为主体，所述主体由平行于所述电介质层的平面中的具有在所述主体外部的曲率中心的至少一个曲面限定基材表面。根据另一种结构，存储电极形成为由具有两个相邻平面的至少一组限定的主体，两个平面相对于基板表面垂直延伸，两个平面的法线相交点位于外部身体。

8. 发明申请

US20050277295A1 Coating process for patterned substrate surfaces 有权
标题翻译：图案化衬底表面的涂覆工艺
公开(公告)号：US20050277295A1
公开(公告)日：2005-12-15
申请号：US11147892
申请日：2005-06-08
申请人： Thomas Hecht , Stefan Jakschik , Uwe Schroder
发明人： Thomas Hecht , Stefan Jakschik , Uwe Schroder
IPC分类号： C23C14/04 , C23C16/02 , C23C16/04 , C23C16/40 , H01L21/20 , H01L21/283 , H01L21/285 , H01L21/31 , H01L21/314 , H01L21/44 , H01L21/469 , H01L21/66 , H01L21/762 , H01L21/768
CPC分类号： C23C16/0281 , C23C14/046 , C23C16/045 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/76877 , H01L22/26
摘要： The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105) which is patterned in a substrate patterning region (102) and has one or more trenches (106) that are to be filled to a predetermined filling height (205), a catalyst layer (201) is introduced into the trenches (106) that are to be filled, a reaction layer (202) is deposited catalytically in the trenches (106) that are to be filled, the catalytically deposited reaction layer (202) is densified in the trenches (106) that are to be filled, and the introduction of the catalyst layer (201) and the catalytic deposition of the reaction layer (202) are repeated until the trenches (106) that are to be filled have been filled to the predetermined filling height (205).
摘要翻译：本发明提供一种用于图案化衬底表面的涂覆方法，其中提供衬底（101），该衬底具有在衬底图案化区域（102）中被图案化并具有一个或多个沟槽（106）的表面（105）将其填充到预定的填充高度（205），将催化剂层（201）引入要填充的沟槽（106）中，在沟槽（106）中催化沉积反应层（202），其中要填充的催化沉积反应层（202）在要填充的沟槽（106）中致密化，并且重复引入催化剂层（201）和催化沉积反应层（202）直到要填充的沟槽（106）已经被填充到预定填充高度（205）。

9. 发明授权

US07531406B2 Method for fabricating an electrical component 有权
标题翻译：电气部件的制造方法
公开(公告)号：US07531406B2
公开(公告)日：2009-05-12
申请号：US11399811
申请日：2006-04-07
申请人： Alejandro Avellan , Thomas Hecht , Stefan Jakschik , Uwe Schroeder
发明人： Alejandro Avellan , Thomas Hecht , Stefan Jakschik , Uwe Schroeder
IPC分类号： H01L21/8234
CPC分类号： H01L28/65 , H01L27/1087 , H01L29/66181
摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.
摘要翻译：制造诸如DRAM半导体存储器或场效应晶体管的电气部件。制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。

10. 发明申请

US20060275981A1 Memory and method for fabricating it 审中-公开
标题翻译：记忆及其制作方法
公开(公告)号：US20060275981A1
公开(公告)日：2006-12-07
申请号：US11442602
申请日：2006-05-30
申请人： Alejandro Avellan , Matthias Goldbach , Thomas Hecht , Stefan Jakschik , Andreas Orth , Uwe Schroder , Michael Stadtmueller , Olaf Storbeck
发明人： Alejandro Avellan , Matthias Goldbach , Thomas Hecht , Stefan Jakschik , Andreas Orth , Uwe Schroder , Michael Stadtmueller , Olaf Storbeck
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/10867
摘要： Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.
摘要翻译：存储器及其制造方法在半导体衬底中形成为集成电路并具有存储电容器和开关晶体管的存储器。存储电容器形成在沟槽中的半导体衬底中，并且具有围绕沟槽形成的外部电极层，体现在沟槽壁上的电介质中间层和内部电极层，沟槽是基本上填充，并且开关晶体管形成在表面区域中的半导体衬底中，并且具有第一源极/漏极掺杂区域，第二源极/漏极掺杂区域和中间沟道，其通过绝缘体层与栅电极分离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式