专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07176514B2 Method and configuration for reinforcement of a dielectric layer at defects by self-aligning and self-limiting electrochemical conversion of a substrate material 有权
标题翻译：通过衬底材料的自对准和自限制电化学转换来加强缺陷处的介电层的方法和结构
公开(公告)号：US07176514B2
公开(公告)日：2007-02-13
申请号：US10413812
申请日：2003-04-15
申请人： Thomas Hecht , Albert Birner , Harald Seidl , Uwe Schröder , Stefan Jakschik , Martin Gutsche
发明人： Thomas Hecht , Albert Birner , Harald Seidl , Uwe Schröder , Stefan Jakschik , Martin Gutsche
IPC分类号： H01L27/108 , H01L21/76
CPC分类号： H01L21/02238 , C25D11/02 , C25D11/32 , H01L21/02258 , H01L21/31675 , H01L21/31687 , H01L27/1085
摘要： A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.
摘要翻译：用于在由导电基板材料制成的基板上制造介电层的方法包括至少通过导电基板材料的自对准和自限制电化学转换为不导电的方式减少流过电介质层的缺陷的漏电流衬底跟随材料在与缺陷相邻的衬底的部分中。还提供了包括具有缺陷的电介质层，由导电基板材料制成的基板以及由与该缺陷相邻的部分中的非导电性基板追随材料制成的加强区域的结构。

2. 发明授权

US07157371B2 Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices 有权
标题翻译：阻挡层以及在制造半导体器件期间抑制扩散过程的方法
公开(公告)号：US07157371B2
公开(公告)日：2007-01-02
申请号：US10653599
申请日：2003-09-02
申请人： Thomas Hecht , Uwe Schroeder , Harald Seidl , Martin Gutsche , Stefan Jakschik , Stephan Kudelka , Albert Birner
发明人： Thomas Hecht , Uwe Schroeder , Harald Seidl , Martin Gutsche , Stefan Jakschik , Stephan Kudelka , Albert Birner
IPC分类号： H01L21/44
CPC分类号： H01L27/11502 , H01L21/02178 , H01L21/02181 , H01L21/28061 , H01L21/31138 , H01L21/31604 , H01L21/3162 , H01L21/76802 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L27/11507 , H01L28/57 , H01L29/0895 , H01L29/4941
摘要： A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.
摘要翻译：由金属氧化物构成的电介质阻挡层通过在不同结构的基底衬底上的分子单层中的顺序气相沉积或分子束外延处理半导体器件的过程中以小于20纳米的厚度施加。该方法允许间隔地从电介质材料形成有效的导电扩散阻挡层，优化阻挡层的层厚度，随后的工艺步骤的温度预算的增加以及用于去除临时阻隔层。

3. 发明申请

US20050127421A1 Semiconductor module having an insulation layer and method for fabricating a semiconductor module having an insulation layer 审中-公开
标题翻译：具有绝缘层的半导体模块和具有绝缘层的半导体模块的制造方法
公开(公告)号：US20050127421A1
公开(公告)日：2005-06-16
申请号：US10502930
申请日：2003-01-16
申请人： Harald Seidl , Jorn Lutzen , Gerhard Beitel , Thomas Hecht , Annette Sanger , Albert Birner
发明人： Harald Seidl , Jorn Lutzen , Gerhard Beitel , Thomas Hecht , Annette Sanger , Albert Birner
IPC分类号： H01L21/02 , H01L21/28 , H01L21/314 , H01L21/8242 , H01L29/51 , H01L27/108
CPC分类号： H01L21/28194 , H01L21/02175 , H01L21/02282 , H01L21/314 , H01L27/1085 , H01L27/10861 , H01L27/10873 , H01L28/40 , H01L29/517
摘要： A semiconductor module is described which is essentially constructed from a silicon material and has an insulation layer for example in the form of a gate insulation layer or a MOS transistor or in the form of an insulation layer of a memory cell for a dynamic memory module. The insulation layer preferably comprises a dielectric material whose band gap is greater than the band gap of SiO2. To construct the insulation layer, use is made of materials which have a metal-fluorine compound, such as e.g. lithium fluoride. Particularly thin insulation layers are provided by the material described.
摘要翻译：描述了一种半导体模块，其基本上由硅材料构成，并且具有例如栅极绝缘层或MOS晶体管形式的绝缘层，或以动态存储器模块的存储单元的绝缘层的形式。绝缘层优选地包括其带隙大于SiO 2带隙的电介质材料。为了构造绝缘层，使用具有金属 - 氟化合物的材料，例如，氟化锂。通过所述材料提供特别薄的绝缘层。

4. 发明申请

US20070034927A1 Trench storage capacitor 审中-公开
标题翻译：沟槽存储电容
公开(公告)号：US20070034927A1
公开(公告)日：2007-02-15
申请号：US11272038
申请日：2005-11-14
申请人： Harald Seidl , Dirk Manger , Matthias Goldbach , Albert Birner , Stefan Slesazeck
发明人： Harald Seidl , Dirk Manger , Matthias Goldbach , Albert Birner , Stefan Slesazeck
IPC分类号： H01L29/94
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/945
摘要： A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a “buried” collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.
摘要翻译：沟槽存储电容器包括一掩埋板，其被掺杂的硅层延伸到芯套绝缘层的正上方。沟槽存储电容器的导体层优选地应用于“埋入”的轴环绝缘层，并借助于由ALD制成的保护层进行掩模。在示例性实施例中，导体层由非晶硅组成，其被用作下沟槽区域中的HSG层。

5. 发明申请

US20050158945A1 Memory cell and method for fabricating it 有权
标题翻译：记忆单元及其制造方法
公开(公告)号：US20050158945A1
公开(公告)日：2005-07-21
申请号：US10980069
申请日：2004-11-03
申请人： Albert Birner , Matthias Foerster , Thomas Hecht , Michael Stadtmueller , Andreas Orth
发明人： Albert Birner , Matthias Foerster , Thomas Hecht , Michael Stadtmueller , Andreas Orth
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8229 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L29/945
摘要： The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-type depression (102), grain elements (104) being grown on the inner areas of the trench-type depression (102), a dielectric layer (202) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements (104) growing selectively on the inner areas (105) of the trench-type depression (102) in an electrode region (301) forming a lower region of the trench-type depression (102) and an amorphous silicon layer continuing to grow in a collar region (302) forming an upper region of the trench-type depression (102).
摘要翻译：本发明提供了一种用于制造存储单元的方法，提供了一种衬底（101），蚀刻到衬底（101）中的沟槽型凹陷（102），在沟槽中非保形地沉积的阻挡层（103）型凹陷（102），在沟槽型凹部（102）的内部区域上生长的晶粒元素（104），沉积在晶粒元素的表面上的介电层（202）和沟槽的内部区域型凹陷，并且导电层沉积在电介质层上，晶粒元素（104）选择性地生长在形成下部区域的电极区域（301）中的沟槽型凹陷（102）的内部区域（105）的沟槽型凹陷（102）和在形成沟槽型凹陷（102）的上部区域的凸缘区域（302）中继续生长的非晶硅层。

6. 发明授权

US06919255B2 Semiconductor trench structure 失效
标题翻译：半导体沟槽结构
公开(公告)号：US06919255B2
公开(公告)日：2005-07-19
申请号：US10630373
申请日：2003-07-30
申请人： Albert Birner , Matthias Goldbach , Thomas Hecht , Lars Heineck , Stephan Kudelka , Jörn Lützen , Dirk Manger , Andreas Orth
发明人： Albert Birner , Matthias Goldbach , Thomas Hecht , Lars Heineck , Stephan Kudelka , Jörn Lützen , Dirk Manger , Andreas Orth
IPC分类号： H01L27/108 , H01L21/00 , H01L21/20 , H01L21/334 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.
摘要翻译：一种制造半导体沟槽结构的方法包括在半导体衬底中形成沟槽并用填充物填充沟槽。具有第一最高温度的第一热处理固化填料。从沟槽的上部区域移除填料至达边界表面限定了一个环形区域。在具有不显着高于第一最高温度的第二最高温度的第二热处理中，衬套沉积在套环区域和边界表面上。将衬垫从边界表面移除，从而暴露填料。然后从沟槽的下部区域去除填料。

7. 发明授权

US07144770B2 Memory cell and method for fabricating it 有权
标题翻译：记忆单元及其制造方法
公开(公告)号：US07144770B2
公开(公告)日：2006-12-05
申请号：US10980069
申请日：2004-11-03
申请人： Albert Birner , Matthias Foerster , Thomas Hecht , Michael Stadtmueller , Andreas Orth
发明人： Albert Birner , Matthias Foerster , Thomas Hecht , Michael Stadtmueller , Andreas Orth
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L29/945
摘要： The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-type depression (102), grain elements (104) being grown on the inner areas of the trench-type depression (102), a dielectric layer (202) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements (104) growing selectively on the inner areas (105) of the trench-type depression (102) in an electrode region (301) forming a lower region of the trench-type depression (102) and an amorphous silicon layer continuing to grow in a collar region (302) forming an upper region of the trench-type depression (102).
摘要翻译：本发明提供了一种用于制造存储单元的方法，提供了一种衬底（101），蚀刻到衬底（101）中的沟槽型凹陷（102），在沟槽中非保形地沉积的阻挡层（103）型凹陷（102），在沟槽型凹部（102）的内部区域上生长的晶粒元素（104），沉积在晶粒元素的表面上的介电层（202）和沟槽的内部区域型凹陷，并且导电层沉积在电介质层上，晶粒元素（104）选择性地生长在形成下部区域的电极区域（301）中的沟槽型凹陷（102）的内部区域（105）的沟槽型凹陷（102）和在形成沟槽型凹陷（102）的上部区域的凸缘区域（302）中继续生长的非晶硅层。

8. 发明授权

US09147610B2 Monitor structures and methods of formation thereof 有权
标题翻译：监测结构及其形成方法
公开(公告)号：US09147610B2
公开(公告)日：2015-09-29
申请号：US13531129
申请日：2012-06-22
申请人： Albert Birner , Tobias Herzig
发明人： Albert Birner , Tobias Herzig
IPC分类号： H01L21/00 , H01L21/768 , H01L21/66 , H01L23/48 , H01L23/31
CPC分类号： H01L22/26 , H01L21/76898 , H01L22/12 , H01L22/20 , H01L22/30 , H01L22/32 , H01L23/3107 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.
摘要翻译：根据本发明的实施例，一种形成电子装置的方法包括在工件中形成第一开口和第二开口。第一个开口比第二个开口更深。该方法还包括在第一开口内形成填充材料以形成通孔的一部分，并在第二开口内形成填充材料。

9. 发明申请

US20130341620A1 Monitor Structures and Methods of Formation Thereof 有权
公开(公告)号：US20130341620A1
公开(公告)日：2013-12-26
申请号：US13531129
申请日：2012-06-22
申请人： Albert Birner , Tobias Herzig
发明人： Albert Birner , Tobias Herzig
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L22/26 , H01L21/76898 , H01L22/12 , H01L22/20 , H01L22/30 , H01L22/32 , H01L23/3107 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

10. 发明授权

US07928481B2 Method and layout of semiconductor device with reduced parasitics 有权
公开(公告)号：US07928481B2
公开(公告)日：2011-04-19
申请号：US11828944
申请日：2007-07-26
申请人： Albert Birner , Qiang Chen
发明人： Albert Birner , Qiang Chen
IPC分类号： H01L29/76
摘要： An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式