专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5572158A Amplifier with active duty cycle correction 失效
标题翻译：具有有效占空比校正功能的放大器
公开(公告)号：US5572158A
公开(公告)日：1996-11-05
申请号：US548900
申请日：1995-09-18
申请人： Thomas H. Lee , Kevin S. Donnelly , Tsyr-Chyang Ho
发明人： Thomas H. Lee , Kevin S. Donnelly , Tsyr-Chyang Ho
IPC分类号： H03K5/08 , H03K3/017
CPC分类号： H03K5/086
摘要： A circuit is provided which actively corrects the duty cycle of a periodic signal such as a clock signal. The amplifier circuit includes a duty cycle error measurement circuit which measures the error of the output signal from a predetermined duty cycle, for example, 50% duty cycle. A correcting signal is generated from the error signal output by the duty cycle error measurement circuit. The correcting signal is combined with the uncorrected input signal to the circuit to function to offset the signal in order to correct the duty cycle, the combined signals are input to an integrating capacitance to generate a slew limited signal. By varying the amount of the correcting signal and therefore the symmetry of the slew limited signal, the duty cycle of the output can be varied to generate a signal with the desired duty cycle.
摘要翻译：提供一种电路，其主动地校正诸如时钟信号的周期性信号的占空比。放大器电路包括占空比误差测量电路，其测量来自预定占空比的输出信号的误差，例如50％占空比。由占空比误差测量电路输出的误差信号产生校正信号。校正信号与未校正的输入信号组合到电路以用于偏移信号以便校正占空比，组合信号被输入到积分电容以产生转换限制信号。通过改变校正信号的量并因此改变转换限制信号的对称性，可以改变输出的占空比以产生具有所需占空比的信号。

2. 发明授权

US06340900B1 Phase detector with minimized phase detection error 失效
公开(公告)号：US06340900B1
公开(公告)日：2002-01-22
申请号：US08582045
申请日：1996-01-02
申请人： Kevin S. Donnelly , Thomas H. Lee , Tsyr-Chyang Ho
发明人： Kevin S. Donnelly , Thomas H. Lee , Tsyr-Chyang Ho
IPC分类号： H03K526
CPC分类号： G01R25/00 , H03L7/085
摘要： A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal. The second circuit is cross-coupled to the first circuit such that an error current generated by the second circuit cancels that generated by the first circuit such that the phase detector detects the phase difference between the first and second signals with minimized phase detection error.

3. 发明授权

US5554945A Voltage controlled phase shifter with unlimited range 失效
标题翻译：电压控制移相器，无限范围
公开(公告)号：US5554945A
公开(公告)日：1996-09-10
申请号：US196582
申请日：1994-02-15
申请人： Thomas H. Lee , Kevin S. Donnelly , Tsyr-Chyang Ho
发明人： Thomas H. Lee , Kevin S. Donnelly , Tsyr-Chyang Ho
IPC分类号： H03H11/20 , H03K5/13
CPC分类号： H03H11/20 , H03K2005/00286
摘要： A voltage-controlled phase shift apparatus having an unlimited range for producing an output signal that varies in phase from an input signal by a predetermined phase difference. The phase shift apparatus includes a first delay circuit coupled to receive the input signal, the first delay circuit for outputting a first intermediate signal that is .alpha. degrees out of phase with the input signal, a second intermediate signal that is .beta. degrees out of phase with the first intermediate signal, a third intermediate signal that is 180 degrees out of phase with the first intermediate signal, and a fourth intermediate signal that is 180 degrees out of phase with the second intermediate signal. The phase shift apparatus also includes a phase interpolator circuit coupled to receive a control voltage signal and the first, second, third and fourth intermediate signals, the phase interpolator for phase mixing a selected pair of the first, second, third and fourth intermediate signals in response to the control voltage signal, the phase interpolator for outputting the output signal. A phase selector circuit coupled to the phase interpolator circuit and coupled to receive a phase slope signal and the control voltage signal selects the selected pair in response to the phase slope signal and the control voltage signal such that the output signal varies in phase from the input signal by the predetermined phase difference.
摘要翻译：一种具有无限范围的电压控制相移装置，用于产生与输入信号相位相差预定相位差的输出信号。相移装置包括耦合以接收输入信号的第一延迟电路，用于输出与输入信号异相异步的第一中间信号的第一延迟电路，与相位相差β度的第二中间信号，第一中间信号，与第一中间信号相差180度的第三中间信号，以及与第二中间信号相差180度的第四中间信号。相移装置还包括相位插值器电路，其耦合以接收控制电压信号和第一，第二，第三和第四中间信号，相位内插器，用于将所选择的一对第一，第二，第三和第四中间信号相互混合在对控制电压信号的响应，用于输出输出信号的相位插值器。相位选择器电路，耦合到所述相位内插器电路并被耦合以接收相位斜率信号，并且所述控制电压信号响应于所述相位斜率信号和所述控制电压信号选择所选择的对，使得所述输出信号与所述输入信号信号预定的相位差。

4. 发明授权

US5614855A Delay-locked loop 失效
标题翻译：延迟锁定环路
公开(公告)号：US5614855A
公开(公告)日：1997-03-25
申请号：US512597
申请日：1995-08-21
申请人： Thomas H. Lee , Kevin S. Donnelly , Tsyr-Chyang Ho , Mark G. Johnson
发明人： Thomas H. Lee , Kevin S. Donnelly , Tsyr-Chyang Ho , Mark G. Johnson
IPC分类号： G01R31/28 , H03L7/00 , H03L7/08 , H03L7/081 , H03L7/093 , H03K5/13
CPC分类号： H03L7/0812
摘要： A delay locked loop (DLL) is described in which a phase detector compares the phase of the output of the DLL with that of a reference input. The output of the phase comparator drives a differential charge pump which functions to integrate the phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Because the DLL adjusts the phase shifter until the output of the phase detector is high 50% of the time, on average, the relationship of the DLL output clock to the input reference clock depends only on the type of phase detector used. For example, when a data receiver is used as the phase detector in the DLL, the output of the DLL is a clock signal which can be used as a sampling clock for data receivers elsewhere in the system, and is timed to sample data at the optional instant independent of temperature, supply voltage and process variations. Alternatively, a quadrature phase detector may be employed to generate a clock signal that possesses a quadrature (90.degree. ) relationship with a reference clock signal input. This may be used, for example, to generate a transmit clock for a data transmission device. Furthermore, the DLL is controlled to minimize dither jitter while minimizing acquisition time. In addition, duty cycle correcting amplifiers are employed to produce a DLL output clock that has a desired duty cycle, for example 50%. Additionally, the inputs to the charge pump are reversed in alternate quadrants of the phase plane in order to enable unlimited phase shift with a finite control voltage range.
摘要翻译：描述了延迟锁定环（DLL），其中相位检测器将DLL的输出的相位与参考输入的相位进行比较。相位比较器的输出驱动一个差分电荷泵，用于对相位比较器输出信号随时间进行积分。电荷泵输出控制无限幅度的移相器，可调节DLL输出的相位，使相位比较器的输出平均高达50％的时间。因为DLL调整移相器，直到相位检测器的输出高达50％的时间，平均而言，DLL输出时钟与输入参考时钟的关系仅取决于所使用的相位检测器的类型。例如，当数据接收器用作DLL中的相位检测器时，DLL的输出是可以用作系统中其他地方的数据接收器的采样时钟的时钟信号，并且被定时以在可选速度独立于温度，电源电压和工艺变化。或者，可以采用正交相位检测器来产生与参考时钟信号输入具有正交（90°）关系的时钟信号。这可以用于例如为数据传输设备产生传输时钟。此外，DLL被控制以最小化抖动抖动，同时最小化采集时间。此外，采用占空比校正放大器来产生具有期望占空比的DLL输出时钟，例如50％。此外，电荷泵的输入在相平面的交替象限中反转，以便在有限的控制电压范围内实现无限相移。

5. 发明授权

US06642746B2 Phase detector with minimized phase detection error 失效
公开(公告)号：US06642746B2
公开(公告)日：2003-11-04
申请号：US10247878
申请日：2002-09-20
申请人： Kevin S. Donnelly , Thomas H. Lee , Tsyr-Chyang Ho
发明人： Kevin S. Donnelly , Thomas H. Lee , Tsyr-Chyang Ho
IPC分类号： H03K526
CPC分类号： H03D13/008
摘要： A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal. The second circuit is cross-coupled to the first circuit such that an error current generated by the second circuit cancels that generated by the first circuit such that the phase detector detects the phase difference between the first and second signals with minimized phase detection error.

6. 发明授权

US06480035B1 Phase detector with minimized phase detection error 有权
标题翻译：相位检测器，具有最小的相位检测误差
公开(公告)号：US06480035B1
公开(公告)日：2002-11-12
申请号：US09707491
申请日：2000-11-06
申请人： Kevin S. Donnelly , Thomas H. Lee , Tsyr-Chyang Ho
发明人： Kevin S. Donnelly , Thomas H. Lee , Tsyr-Chyang Ho
IPC分类号： H03K526
CPC分类号： G01R25/00 , H03L7/085
摘要： A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal. The second circuit is cross-coupled to the first circuit such that an error current generated by the second circuit cancels that generated by the first circuit such that the phase detector detects the phase difference between the first and second signals with minimized phase detection error.
摘要翻译：描述了一种相位检测器，其包括呈现高差分阻抗和低共模阻抗的负载电路。负载电路耦合到（1）电源和（2）第一节点和第二节点。第一和第二节点形成相位检测器的输出。电容电路具有（1）耦合到第一节点和地的第一电容器和（2）耦合到第二节点和地的第二电容器。第一电路耦合到第一和第二节点，用于检测第一信号和第二信号之间的相位差。第二电路耦合到第一和第二节点，用于检测第一和第二信号之间的相位差，并且用于使第一电路的相位检测误差最小化，使得能够以最小相位检测来检测第一和第二信号之间的相位差错误。第一和第二电路中的每一个接收第一和第二信号和参考信号。第二电路交叉耦合到第一电路，使得由第二电路产生的误差电流消除由第一电路产生的误差电流，使得相位检测器以最小的相位检测误差检测第一和第二信号之间的相位差。

7. 发明授权

US07535933B2 Calibrated data communication system and method 有权
标题翻译：校准数据通信系统及方法
公开(公告)号：US07535933B2
公开(公告)日：2009-05-19
申请号：US11327213
申请日：2006-01-05
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.
摘要翻译：一种系统包括第一集成电路装置和第二集成电路装置。第一设备将数据序列发送到第二集成电路设备，并且第二设备对数据序列进行采样以产生接收机数据。然后，第二设备将接收机数据发送回第一设备。在第一集成电路装置内，执行数据序列与接收机数据之间的比较，并且基于比较，第一装置产生表示经校准的定时偏移的信息。第一设备使用代表校准的定时偏移的信息来调整与从第一集成电路向第二集成电路传送写入数据相关联的定时。

8. 发明授权

US08630317B2 Memory system with calibrated data communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US08630317B2
公开(公告)日：2014-01-14
申请号：US13447080
申请日：2012-04-13
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06 , G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
摘要翻译：集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

9. 发明申请

US20120204054A1 Memory System with Calibrated Data Communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US20120204054A1
公开(公告)日：2012-08-09
申请号：US13447080
申请日：2012-04-13
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
摘要翻译：集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

10. 发明申请

US20090327789A1 Memory System with Calibrated Data Communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US20090327789A1
公开(公告)日：2009-12-31
申请号：US12430836
申请日：2009-04-27
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： G06F11/00 , G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.
摘要翻译：一种系统包括第一集成电路装置和第二集成电路装置。第一设备将数据序列发送到第二集成电路设备，并且第二设备对数据序列进行采样以产生接收机数据。然后，第二设备将接收机数据发送回第一设备。在第一集成电路装置内，执行数据序列与接收机数据之间的比较，并且基于比较，第一装置产生表示经校准的定时偏移的信息。第一设备使用代表校准的定时偏移的信息来调整与从第一集成电路向第二集成电路传送写入数据相关联的定时。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式