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1. 发明授权

US6115761A First-In-First-Out (FIFO) memories having dual descriptors and credit passing for efficient access in a multi-processor system environment 失效
标题翻译：先进先出（FIFO）存储器具有双描述符和信用传递，以便在多处理器系统环境中有效地访问
公开(公告)号：US6115761A
公开(公告)日：2000-09-05
申请号：US865737
申请日：1997-05-30
申请人： Thomas Daniel , Anil Gupta
发明人： Thomas Daniel , Anil Gupta
IPC分类号： G06F15/167 , G06F5/00 , G06F12/06
CPC分类号： G06F15/167
摘要： To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.
摘要翻译：为了减少跨处理器系统中的系统总线的FIFO访问周期，在多处理器系统中，两个处理器通过FIFO通过系统总线进行通信，则提供两个独立的FIFO描述符。第一描述符由位于板上的处理器由FIFO维护，第二描述符由通过总线与FIFO通信的板外处理器来维护。当一个处理器执行FIFO操作时，处理器通过总线上的存储器访问来更新其他处理器的描述符。此外，一个模块向另一个模块传递信用以指示后者具有连续执行多个FIFO操作的许可。在一个实施例中，使用特殊的非有效数据值来指示空的FIFO位置。

2. 发明授权

US06615296B2 Efficient implementation of first-in-first-out memories for multi-processor systems 有权
标题翻译：高效地实现多处理器系统的先进先出存储器
公开(公告)号：US06615296B2
公开(公告)日：2003-09-02
申请号：US09881512
申请日：2001-06-14
申请人： Thomas Daniel , Anil Gupta
发明人： Thomas Daniel , Anil Gupta
IPC分类号： G06F1320
CPC分类号： G06F15/167
摘要： To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.
摘要翻译：为了减少跨处理器系统中的系统总线的FIFO访问周期，在多处理器系统中，两个处理器通过FIFO通过系统总线进行通信，则提供两个独立的FIFO描述符。第一描述符由位于板上的处理器由FIFO维护，第二描述符由通过总线与FIFO通信的板外处理器来维护。当一个处理器执行FIFO操作时，处理器通过总线上的存储器访问来更新其他处理器的描述符。此外，一个模块向另一个模块传递信用以指示后者具有连续执行多个FIFO操作的许可。在一个实施例中，使用特殊的非有效数据值来指示空的FIFO位置。

3. 发明授权

US5987258A Register reservation method for fast context switching in microprocessors 失效
标题翻译：微处理器快速上下文切换的注册预约方法
公开(公告)号：US5987258A
公开(公告)日：1999-11-16
申请号：US883137
申请日：1997-06-27
申请人： Thomas Daniel , Anil Gupta
发明人： Thomas Daniel , Anil Gupta
IPC分类号： G06F9/46 , G06F9/45
CPC分类号： G06F9/462
摘要： Microprocessor main programs and their interrupt handling routines are written in a high level programming language such as C. Each is compiled separately, and each is compiled invoking a compiler option which commands the compiler to not use a given set of registers in the compiled code. Post-processing is then performed on the compiled interrupt code to replace accesses to a first set of registers with accesses to the given set of registers. The result is that while both the main program and the interrupt handler were written in C, the compiled code for each employs different registers. This allows context switching from the main program to the interrupt handler and back again with almost none of the overhead traditionally associated with context switching register save and restore operations during exception handling.
摘要翻译：微处理器主程序及其中断处理例程以高级编程语言（如C）编写。每个编译单独编译，每个编译调用编译器选项，命令编译器在编译代码中不使用给定的一组寄存器。然后对编译的中断代码进行后处理，以通过访问给定的寄存器组来替换对第一组寄存器的访问。结果是当主程序和中断处理程序都用C编写时，每个编译代码使用不同的寄存器。这允许从主程序到中断处理程序的上下文切换，并且在异常处理期间几乎没有传统上与上下文切换寄存器保存和恢复操作相关联的开销。

4. 发明授权

US06493773B1 Data validity measure for efficient implementation of first-in-first-out memories for multi-processor systems 有权
标题翻译：有效实施多处理器系统先进先出存储器的数据有效性测量
公开(公告)号：US06493773B1
公开(公告)日：2002-12-10
申请号：US09713998
申请日：2000-11-15
申请人： Thomas Daniel , Anil Gupta
发明人： Thomas Daniel , Anil Gupta
IPC分类号： G06F1314
CPC分类号： G06F15/167
摘要： To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.
摘要翻译：为了减少跨处理器系统中的系统总线的FIFO访问周期，在多处理器系统中，两个处理器通过FIFO通过系统总线进行通信，则提供两个独立的FIFO描述符。第一描述符由位于板上的处理器由FIFO维护，第二描述符由通过总线与FIFO通信的板外处理器来维护。当一个处理器执行FIFO操作时，处理器通过总线上的存储器访问来更新其他处理器的描述符。此外，一个模块向另一个模块传递信用以指示后者具有连续执行多个FIFO操作的许可。在一个实施例中，使用特殊的非有效数据值来指示空的FIFO位置。

5. 发明授权

US08879458B2 Transmission in a network with active and sleeping clients 有权
标题翻译：在主动和睡眠客户端的网络中传输
公开(公告)号：US08879458B2
公开(公告)日：2014-11-04
申请号：US13453664
申请日：2012-04-23
申请人： Anil Gupta , Sung-Ju Lee
发明人： Anil Gupta , Sung-Ju Lee
IPC分类号： H04H20/71 , G08C17/00 , H04W4/00 , H04L12/28
CPC分类号： H04H20/423 , H04L12/189 , H04L47/14 , H04L47/15 , H04L65/4076 , H04N21/6405 , H04W4/06 , H04W52/0216 , H04W52/0219 , H04W72/005 , H04W76/28 , H04W76/40 , Y02D70/142
摘要： Methods, devices, and machine readable media are provided for transmission in a network with active and sleeping clients. Some examples can include transmitting a first multicast stream of data in response to an active wireless client being associated with the wireless network device at a particular time. The method can include transmitting a second multicast stream of the data after the first multicast stream in response to a sleeping wireless client being associated with the wireless network device at the particular time and in response to a delivery traffic indication message count expiring. The first and/or second multicast streams of the data can be retransmitted a number of times (e.g., at different data rates). An active/sleep status can be maintained for the wireless clients. A unicast stream can be transmitted when the number of clients does not exceed a threshold.
摘要翻译：提供方法，设备和机器可读介质用于在具有主动和睡眠客户端的网络中进行传输。一些示例可以包括响应于在特定时间与无线网络设备相关联的活动无线客户端来发送数据的第一多播流。所述方法可以包括在所述特定时间响应于与所述无线网络设备相关联的睡眠无线客户端以及响应于传送通信量指示消息计数到期而在所述第一多播流之后发送所述数据的第二多播流。可以多次重复数据的第一和/或第二多播流（例如，以不同的数据速率）。可以为无线客户端维护活动/睡眠状态。当客户端的数量不超过阈值时，可以传输单播流。

6. 发明申请

US20130346671A1 On-Chip Bad Block Management for NAND Flash Memory 有权
标题翻译：用于NAND闪存的片上坏块管理
公开(公告)号：US20130346671A1
公开(公告)日：2013-12-26
申请号：US13530518
申请日：2012-06-22
申请人： Oron Michael , Robin John Jigour , Anil Gupta
发明人： Oron Michael , Robin John Jigour , Anil Gupta
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0679 , G06F2212/7201
摘要： Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.
摘要翻译：关于创建和使用用于坏块映射的查找表的某些功能可以在存储器设备本身中“在芯片上”实现，即在附加电路中的相同裸片上，或者甚至在命令和控制逻辑存储设备，以减少开销。此外，查找表的片上实现可以与命令和控制逻辑的其他功能紧密集成，以实现NAND闪存的强大的新命令，例如连续读取命令及其变体。

7. 发明授权

US08279897B2 Synchronization in a wireless node 有权
标题翻译：无线节点中的同步
公开(公告)号：US08279897B2
公开(公告)日：2012-10-02
申请号：US12715774
申请日：2010-03-02
申请人： Jung Gun Lee , Raul Herman Etkin , Sung-Ju Lee , Anil Gupta , Vincent Ma
发明人： Jung Gun Lee , Raul Herman Etkin , Sung-Ju Lee , Anil Gupta , Vincent Ma
IPC分类号： H04J3/06 , H04L7/00 , H04B15/00
CPC分类号： H04J3/06 , H04L43/00 , H04W56/0015
摘要： A wireless node receives a beacon from a wireless access point. The beacon includes a wireless protocol time synchronization function (TSF) timestamp generated with reference to a global clock for a network. The wireless node synchronizes a counter according to the TSF timestamp. The wireless node receives a global timing offset (GTO) packet from the wireless access point and combines the GTO packet with a counter value to generate a global timestamp.
摘要翻译：无线节点从无线接入点接收信标。信标包括参考网络的全局时钟生成的无线协议时间同步功能（TSF）时间戳。无线节点根据TSF时间戳同步计数器。无线节点从无线接入点接收全局定时偏移（GTO）分组，并将GTO分组与计数器值组合以产生全局时间戳。

8. 发明申请

US20110211518A1 ADAPTIVE WIRELESS NETWORK 有权
标题翻译：自适应无线网络
公开(公告)号：US20110211518A1
公开(公告)日：2011-09-01
申请号：US12896397
申请日：2010-10-01
申请人： Anil Gupta , Sung-Ju Lee , Vincent Ma
发明人： Anil Gupta , Sung-Ju Lee , Vincent Ma
IPC分类号： H04H20/71
CPC分类号： H04H20/63 , H04W28/18 , H04W84/12 , H04W88/08
摘要： Systems, methods, and devices are provided for an adaptive wireless network. A wireless network device for an adaptive wireless network can include an application specific integrated circuit (ASIC) including logic and memory resources coupled to the ASIC. The logic can store information received from a number of clients associated with the wireless network device regarding capabilities of the number of clients in the memory resources. The logic can adapt a guard interval and/or a channel width for transmission of a data stream according to capabilities of a number of clients associated with the wireless network device.
摘要翻译：为自适应无线网络提供系统，方法和设备。用于自适应无线网络的无线网络设备可以包括专用集成电路（ASIC），其包括耦合到ASIC的逻辑和存储器资源。逻辑可以存储从与无线网络设备相关联的多个客户端接收的关于存储器资源中的客户端数量的能力的信息。该逻辑可以根据与无线网络设备相关联的多个客户端的能力来调整用于传输数据流的保护间隔和/或信道宽度。

9. 发明申请

US20090141542A1 MRAM DESIGN WITH LOCAL WRITE CONDUCTORS OF REDUCED CROSS-SECTIONAL AREA 有权
标题翻译： MRAM设计与减少交叉区域的本地写入导体
公开(公告)号：US20090141542A1
公开(公告)日：2009-06-04
申请号：US11949693
申请日：2007-12-03
申请人： Krishnakumar Mani , Jannier Maximo Roiz Wilson , Anil Gupta , Kimihiro Satoh
发明人： Krishnakumar Mani , Jannier Maximo Roiz Wilson , Anil Gupta , Kimihiro Satoh
IPC分类号： G11C11/02
CPC分类号： G11C11/15 , G11C7/18 , Y10S977/935
摘要： Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a group of memory cells.
摘要翻译：本发明的实施例公开了一种具有分组成多个磁存储器单元的MRAM器件和用于承载写入电流以写入存储器单元的写导体，其中写入导体中的至少一些具有减小的横截面积一组存储单元的附近。

10. 发明授权

US07353325B2 Wear leveling techniques for flash EEPROM systems 失效
标题翻译：闪存EEPROM系统的磨损均衡技术
公开(公告)号：US07353325B2
公开(公告)日：2008-04-01
申请号：US11028882
申请日：2005-01-03
申请人： Karl M. J. Lofgren , Robert D. Norman , Gregory B. Thelin , Anil Gupta
发明人： Karl M. J. Lofgren , Robert D. Norman , Gregory B. Thelin , Anil Gupta
IPC分类号： G06F12/02
CPC分类号： G11C16/3495 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C8/12 , G11C16/349
摘要： A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.
摘要翻译：由闪存电可擦除和可编程只读存储器（“EEPROM”）组成的块的大容量存储系统被组合成块，这些块又被分组到存储体中，以便管理存储器经历的擦除和重写周期的数量银行为了延长内存系统的使用寿命。由于这种类型的存储器单元在有限数量的擦除和重写周期之后变得不可用，尽管在数万个周期中，避免了不均匀地使用存储器组，使得整个存储器不会变得不起作用，因为它的一个存储体具有达到了终点，而其他银行也没有被使用。监视存储器组的相对使用，并且响应于不均匀使用的检测，使它们的物理地址彼此周期性交换，以便在存储器的使用寿命期内甚至使用它们。

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