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1. 发明授权

US06545900B2 MRAM module configuration 有权
公开(公告)号：US06545900B2
公开(公告)日：2003-04-08
申请号：US09951242
申请日：2001-09-12
申请人： Thomas Böhm , Dietmar Gogl , Martin Freitag , Stefan Lammers
发明人： Thomas Böhm , Dietmar Gogl , Martin Freitag , Stefan Lammers
IPC分类号： G11C1702
CPC分类号： G11C11/16 , G11C5/025 , H01L27/222
摘要： An MRAM module configuration in which, in order to increase the packing density, memory cell zones containing memory arrays and peripheral circuits are nested in one another. In this manner, an increased packing density of the memory cell is achieved which results in lowered production costs and a smaller chip space for a more compact configuration.

2. 发明授权

US06577527B2 Method for preventing unwanted programming in an MRAM configuration 失效
公开(公告)号：US06577527B2
公开(公告)日：2003-06-10
申请号：US09999324
申请日：2001-10-31
申请人： Martin Freitag , Stefan Lammers , Dietmar Gogl , Thomas Roehr
发明人： Martin Freitag , Stefan Lammers , Dietmar Gogl , Thomas Roehr
IPC分类号： G11C1100
CPC分类号： G11C11/16 , B82Y10/00
摘要： Unwanted programming by stray magnetic fields is prevented in an MRAM configuration. Compensating currents that counteract the stray magnetic fields are strategically conducted through the MRAM configuration.

3. 发明授权

US06744662B2 Magnetoresistive memory (MRAM) 失效
标题翻译：磁阻记忆体（MRAM）
公开(公告)号：US06744662B2
公开(公告)日：2004-06-01
申请号：US10436428
申请日：2003-05-12
申请人： Martin Freitag , Dietmar Gogl , Heinz Hoenigschmid , Stefan Lammers
发明人： Martin Freitag , Dietmar Gogl , Heinz Hoenigschmid , Stefan Lammers
IPC分类号： G11C1100
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/16
摘要： The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.
摘要翻译：多个磁存储器单元的单元阵列的引线的形式通过偏离引线的正方形横截面而被优化，使得位于单元阵列平面中的写入电流的磁场分量充分快速地减小，增加距离交叉点的距离。单元阵列由列引线和行引线的矩阵构成。

4. 发明授权

US06639829B2 Configuration and method for the low-loss writing of an MRAM 有权
公开(公告)号：US06639829B2
公开(公告)日：2003-10-28
申请号：US09922471
申请日：2001-08-03
申请人： Dietmar Gogl , Helmut Kandolf , Stefan Lammers
发明人： Dietmar Gogl , Helmut Kandolf , Stefan Lammers
IPC分类号： G11C1100
CPC分类号： G11C5/063 , G11C11/15 , G11C11/16
摘要： A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells between a selected word/bit line and the individual bit line/word lines is minimal. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the memory cell and voltages at the bit/word lines are set to minimize a cell voltage across the memory cells between a selected word/bit line and individual bit/word lines. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the particular cell, and, when a voltage V1 and a voltage V2

5. 发明授权

US07239537B2 Method and apparatus for current sense amplifier calibration in MRAM devices 有权
标题翻译：用于MRAM器件中电流检测放大器校准的方法和装置
公开(公告)号：US07239537B2
公开(公告)日：2007-07-03
申请号：US10905585
申请日：2005-01-12
申请人： John K. DeBrosse , Dietmar Gogl , Stefan Lammers , Hans Viehmann
发明人： John K. DeBrosse , Dietmar Gogl , Stefan Lammers , Hans Viehmann
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/1204
摘要： A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.
摘要翻译：校准磁性随机存取存储器（MRAM）电流检测放大器包括与第一负载装置并联的第一多个调整晶体管，第一负载装置与读出放大器的数据侧相关联。与第二负载装置并联地选择性地配置第二组微调晶体管，第二负载装置与感测放大器的参考侧相关联。单独激活第一和第二多个微调晶体管，以补偿相对于读出放大器的数据和参考侧的器件失配。

6. 发明申请

US20060152970A1 METHOD AND APPARATUS FOR CURRENT SENSE AMPLIFIER CALIBRATION IN MRAM DEVICES 有权
标题翻译： MRAM器件中电流检测放大器校准的方法和装置
公开(公告)号：US20060152970A1
公开(公告)日：2006-07-13
申请号：US10905585
申请日：2005-01-12
申请人： John DeBrosse , Dietmar Gogl , Stefan Lammers , Hans Viehmann
发明人： John DeBrosse , Dietmar Gogl , Stefan Lammers , Hans Viehmann
IPC分类号： G11C11/14
CPC分类号： G11C11/16 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/1204
摘要： A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.
摘要翻译：校准磁性随机存取存储器（MRAM）电流检测放大器包括与第一负载装置并联的第一多个调整晶体管，第一负载装置与读出放大器的数据侧相关联。与第二负载装置并联地选择性地配置第二组微调晶体管，第二负载装置与感测放大器的参考侧相关联。单独激活第一和第二多个微调晶体管，以补偿相对于读出放大器的数据和参考侧的器件失配。

7. 发明授权

US06781896B2 MRAM semiconductor memory configuration with redundant cell arrays 失效
标题翻译：具有冗余单元阵列的MRAM半导体存储器配置
公开(公告)号：US06781896B2
公开(公告)日：2004-08-24
申请号：US10135416
申请日：2002-04-30
申请人： Stefan Lammers , Dietmar Gogl , Gerhard Müller
发明人： Stefan Lammers , Dietmar Gogl , Gerhard Müller
IPC分类号： G11C700
CPC分类号： G11C29/70
摘要： The MRAM semiconductor memory configuration has MRAM main cell arrays in the form of a crosspoint array or a transistor array together with redundant MRAM cell arrays formed of redundant MRAM memory cells arranged in a plurality of planes and provided on the same chip. The redundant MRAM cell arrays are distributed over the individual planes of the memory matrix or one plane of the memory array is used in its entirety for providing redundant cell arrays.
摘要翻译： MRAM半导体存储器配置具有交叉点阵列或晶体管阵列形式的MRAM主单元阵列以及布置在多个平面中并设置在同一芯片上的冗余MRAM存储单元形成的冗余MRAM单元阵列。冗余MRAM单元阵列分布在存储器矩阵的各个平面上，或者整体使用存储器阵列的一个平面来提供冗余单元阵列。

8. 发明授权

US06473335B2 MRAM configuration 有权
标题翻译： MRAM配置
公开(公告)号：US06473335B2
公开(公告)日：2002-10-29
申请号：US09898222
申请日：2001-07-03
申请人： Thomas Böhm , Helmut Kandolf , Stefan Lammers
发明人： Thomas Böhm , Helmut Kandolf , Stefan Lammers
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.
摘要翻译：描述了一种磁阻随机存取存储器（MRAM）配置，其中线路驱动器电路分别经由连接节点分配给两个存储单元阵列，结果是驱动器电路的面积实际上可以减半。因此，获得节省空间的架构和更有效的MRAM配置。

9. 发明授权

US06429731B2 CMOS voltage divider 有权
标题翻译： CMOS分压器
公开(公告)号：US06429731B2
公开(公告)日：2002-08-06
申请号：US09816934
申请日：2001-03-23
申请人： Thomas Böhm , Robert Esterl , Stefan Lammers , Zoltan Manyoki
发明人： Thomas Böhm , Robert Esterl , Stefan Lammers , Zoltan Manyoki
IPC分类号： G05F1595
CPC分类号： G05F3/242
摘要： A CMOS voltage divider having a first chain containing series-connected MOS transistors of a first conductivity type is described. Each of the MOS transistors have identical geometrical dimensions and, at the same time, each have identical gate-source voltages. The MOS transistors operate in the linear range of their characteristic curve and between opposite ends of the first chain an input voltage to be divided is present and at whose source terminals the voltage fractions can in each case be picked off. Provision is made of a second chain containing series-connected MOS transistors, complementary to the first MOS transistors. The second chain has the same number of transistors as the first MOS transistors and with the same geometrical dimension in each case. The MOS transistors of the first chain are connected to the MOS transistors of the second chain in such a way that each MOS transistor chain generates the gate-source bias voltage for the respective other MOS transistor chain.
摘要翻译：描述了具有包含第一导电类型的串联MOS晶体管的第一链的CMOS分压器。每个MOS晶体管具有相同的几何尺寸，并且同时具有相同的栅源电压。 MOS晶体管在其特性曲线的线性范围内工作，并且在第一链的相对端之间存在待分割的输入电压，并且在每个情况下，其源极端子的电压分数可以被拾取。提供了包含与第一MOS晶体管互补的串联MOS晶体管的第二链。第二链具有与第一MOS晶体管相同数量的晶体管，并且在每种情况下具有相同的几何尺寸。第一链的MOS晶体管以这样的方式连接到第二链的MOS晶体管，使得每个MOS晶体管链为相应的另一个MOS晶体管链产生栅极 - 源极偏置电压。

10. 发明授权

US07158405B2 Semiconductor memory device having a plurality of memory areas with memory elements 有权
标题翻译：具有多个具有存储元件的存储区域的半导体存储器件
公开(公告)号：US07158405B2
公开(公告)日：2007-01-02
申请号：US10190812
申请日：2002-07-08
申请人： Thomas Böhm , Stefan Lammers , Thomas Röhr
发明人： Thomas Böhm , Stefan Lammers , Thomas Röhr
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C8/12
摘要： A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the memory areas. During operation, each selection device can be assigned in a controllable manner to a plurality of memory areas such that selectively each of the selection devices can carry out an addressing and selection in one of the assigned memory areas.
摘要翻译：半导体存储器件具有特别节省空间的存储区域配置，特别是分配给存储区域的选择设备。在操作期间，可以以可控的方式将每个选择装置分配给多个存储区域，使得选择性地每个选择装置可以在分配的存储区域之一中执行寻址和选择。

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