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1. 发明授权

US06577527B2 Method for preventing unwanted programming in an MRAM configuration 失效
公开(公告)号：US06577527B2
公开(公告)日：2003-06-10
申请号：US09999324
申请日：2001-10-31
申请人： Martin Freitag , Stefan Lammers , Dietmar Gogl , Thomas Roehr
发明人： Martin Freitag , Stefan Lammers , Dietmar Gogl , Thomas Roehr
IPC分类号： G11C1100
CPC分类号： G11C11/16 , B82Y10/00
摘要： Unwanted programming by stray magnetic fields is prevented in an MRAM configuration. Compensating currents that counteract the stray magnetic fields are strategically conducted through the MRAM configuration.

2. 发明授权

US06501686B2 Electronic driver circuit for word lines in a memory matrix, and memory apparatus 有权
标题翻译：用于存储矩阵中的字线的电子驱动电路和存储器装置
公开(公告)号：US06501686B2
公开(公告)日：2002-12-31
申请号：US09927556
申请日：2001-08-09
申请人： Thomas Boehm , Thomas Roehr , Dietmar Gogl
发明人： Thomas Boehm , Thomas Roehr , Dietmar Gogl
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C8/10 , G11C11/16
摘要： An electronic driver circuit for word lines in a memory matrix is described. The driver circuit has coded outputs of a driver source, in particular of a current/voltage source, which are switched through to selected word lines. In this context, the word lines are selected in blocks by a control signal, and the outputs of the driver source are connected thereto. The coding of the driver source then selects the respective active word line.
摘要翻译：描述了存储器矩阵中用于字线的电子驱动电路。驱动器电路具有被切换到所选择的字线的驱动器源，特别是电流/电压源的编码输出。在这种情况下，通过控制信号以块为单位选择字线，并且驱动器源的输出与其连接。然后，驱动源的编码选择相应的有效字线。

3. 发明授权

US06791871B2 MRAM configuration 失效
标题翻译： MRAM配置
公开(公告)号：US06791871B2
公开(公告)日：2004-09-14
申请号：US10627904
申请日：2003-07-25
申请人： Martin Freitag , Thomas Roehr
发明人： Martin Freitag , Thomas Roehr
IPC分类号： G11C1100
CPC分类号： H01L27/228 , G11C11/16
摘要： An MRAM configuration has selection transistors and MTJ layer sequences lying in parallel with each other in a memory cell matrix. A considerable space saving can thus be achieved and therefore the MRAM configuration is less expensive to manufacture and has a greater packing density. In addition, the MRAM configuration allows a rapid read access with a minimal area requirement.
摘要翻译： MRAM配置具有在存储单元矩阵中彼此平行的选择晶体管和MTJ层序列。因此可以实现相当多的空间节省，因此MRAM配置制造成本较低并且具有更大的包装密度。此外，MRAM配置允许以最小面积要求进行快速读取访问。

4. 发明授权

US07414257B2 Switching device for configurable interconnect and method for preparing the same 失效
标题翻译：用于可配置互连的交换设备及其制备方法
公开(公告)号：US07414257B2
公开(公告)日：2008-08-19
申请号：US10812991
申请日：2004-03-31
申请人： Thomas D. Happ , Thomas Roehr
发明人： Thomas D. Happ , Thomas Roehr
IPC分类号： H01L29/72
CPC分类号： H01G9/22 , H01G9/025 , H01G11/02 , H01G11/08 , H01G11/32 , H01G11/56 , H01L23/5252 , H01L2924/0002 , Y02E60/13 , H01L2924/00
摘要： The present invention relates to a switching device to be irreversibly switched from an electrically isolating off-state into an electrically conducting on-state for use in a configurable interconnect, comprising two separate electrodes, at least one of which being a reactive metal electrode, and a solid state electrolyte arranged between said electrodes and being capable of electrolyte isolating said electrodes to define said off-state, said electrodes and said solid state electrolyte forming a redox-system having a mini-mum voltage (“turn-on voltage”) to start a redox reaction, the redox reaction resulting in the generation of metal ions to be released into said solid state electrolyte, the metal ions being reduced to increase a metal concentration within said solid state electrolyte, wherein an increase of said metal concentration results in a conductive metallic connection bridging the electrodes to define the on-state.
摘要翻译：本发明涉及一种从电绝缘断开状态不可逆地切换到用于可配置互连中的导电导通状态的开关装置，包括两个单独的电极，其中至少一个电极是反应性金属电极，以及布置在所述电极之间并且能够电解隔离所述电极以限定所述截止状态的固态电解质，所述电极和所述固态电解质形成具有微小电压（“导通电压”）的氧化还原系统，开始氧化还原反应，所述氧化还原反应导致产生将被释放到所述固态电解质中的金属离子，所述金属离子被还原以增加所述固态电解质中的金属浓度，其中所述金属浓度的增加导致导电金属连接桥接电极以限定导通状态。

5. 发明授权

US07355898B2 Integrated circuit and method for reading from resistance memory cells 有权
标题翻译：用于从电阻存储单元读取的集成电路和方法
公开(公告)号：US07355898B2
公开(公告)日：2008-04-08
申请号：US11227429
申请日：2005-09-16
申请人： Thomas Roehr
发明人： Thomas Roehr
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C13/0011 , G11C7/12 , G11C13/0026 , G11C13/004 , G11C2013/0042 , G11C2213/15 , G11C2213/79
摘要： A method and apparatus for reading from a memory arrangement, in particular, for reading from a CBRAM or another memory arrangement based on resistively switching memory cells includes charging a bit line to a voltage value, discharging the bit line by a cell resistance, and subsequently assessing a resulting voltage difference in a measuring device, in particular, a differential sense amplifier.
摘要翻译：特别地，用于从存储器装置读取的方法和装置，特别是用于基于电阻切换存储器单元从CBRAM或另一存储器装置读取的方法和装置包括将位线充电到电压值，将位线排出单元电阻，以及随后评估测量装置，特别是差分读出放大器中产生的电压差。

6. 发明授权

US07257013B2 Method for writing data into a memory cell of a conductive bridging random access memory, memory circuit and CBRAM memory circuit 有权
公开(公告)号：US07257013B2
公开(公告)日：2007-08-14
申请号：US11222282
申请日：2005-09-08
申请人： Thomas Roehr
发明人： Thomas Roehr
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0069 , G11C2013/009 , G11C2213/79
摘要： The present invention refers to a method for writing data into a memory cell of a conductive bridging random access memory and to a memory circuit comprising memory cells with programmable metallization cells, particularly a CBRAM memory circuit. The embodiments of the prevent invention provide a method and a memory circuit for holding adjacently arranged bit lines at writing voltages during a writing operation of a selected memory cell to reduce voltage crosstalk.

7. 发明授权

US07215568B2 Resistive memory arrangement 有权
标题翻译：电阻记忆布置
公开(公告)号：US07215568B2
公开(公告)日：2007-05-08
申请号：US11215443
申请日：2005-08-30
申请人： Corvin Liaw , Thomas Roehr , Michael Kund
发明人： Corvin Liaw , Thomas Roehr , Michael Kund
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0011 , G11C2213/78 , G11C2213/79
摘要： Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.
摘要翻译：提供了具有以行和列构成的单元阵列并且具有连接到用于驱动的驱动元件的电阻性存储单元的电阻式存储器装置。每个驱动元件共同连接到形成存储单元的n个单元电阻器，单元电阻器是CBRAM电阻元件，特别是与CBRAM电阻元件实现的用于电阻存储器布置的写入，读取和擦除方法。

8. 发明申请

US20070002645A1 METHOD FOR PROGRAMMING MULTI-BIT CHARGE-TRAPPING MEMORY CELL ARRAYS 有权
标题翻译：用于编程多位电荷捕获存储器单元阵列的方法
公开(公告)号：US20070002645A1
公开(公告)日：2007-01-04
申请号：US11172421
申请日：2005-06-30
申请人： Thomas Roehr , Josef Willer
发明人： Thomas Roehr , Josef Willer
IPC分类号： G11C7/00
CPC分类号： G11C16/12
摘要： A programming voltage is applied to source and drain in order to generate hot-hole injection at one end of the channel of a memory cell. The undesired programming of a neighboring memory cell is avoided by the application of an intermediate inhibit voltage to an adjacent bitline. This is done by precharging all the bitlines to the inhibit voltage, either by successively applying the inhibit voltage to every bitline individually or by applying both the upper and the lower programming voltage to one half of the bitlines and then short-circuiting all the bitlines to produce an intermediate voltage.
摘要翻译：将编程电压施加到源极和漏极，以便在存储器单元的沟道的一端产生热空穴注入。通过向相邻位线施加中间禁止电压来避免相邻存储器单元的不期望的编程。这可以通过将所有位线预充电到抑制电压来完成，方法是通过将禁止电压单独地连续施加到每个位线，或者通过将上限和下限编程电压同时施加到位线的一半，然后将所有位线短路到产生中间电压。

9. 发明申请

US20060060832A1 Memory component with memory cells having changeable resistance and fabrication method therefor 失效
标题翻译：具有可变电阻的存储单元的存储器组件及其制造方法
公开(公告)号：US20060060832A1
公开(公告)日：2006-03-23
申请号：US11214692
申请日：2005-08-29
申请人： Ralf Symanczyk , Thomas Roehr
发明人： Ralf Symanczyk , Thomas Roehr
IPC分类号： H01L47/00
CPC分类号： H01L45/143 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/1675 , Y10S438/90
摘要： The invention relates to a memory component having memory cells based on an active solid electrolyte material which can be changed in terms of its resistance value. The active solid electrolyte material is embedded between a bottom and top electrode, can be switched between an on state with a low resistance and an off state with a high resistance by comparison therewith by application of a suitable electric field between said electrodes. A resistance material is embedded in parallel with the solid electrolyte material between the electrodes.
摘要翻译：本发明涉及具有可根据其电阻值改变的活性固体电解质材料的存储单元的存储元件。活性固体电解质材料嵌入在底部和顶部电极之间，可以通过在所述电极之间施加合适的电场而与具有低电阻的导通状态和具有高电阻的断开状态进行比较来进行比较。电阻材料与电极之间的固体电解质材料平行地嵌入。

10. 发明授权

US06950328B2 Imprint suppression circuit scheme 失效
标题翻译：压印抑制电路方案
公开(公告)号：US06950328B2
公开(公告)日：2005-09-27
申请号：US10734439
申请日：2003-12-11
申请人： Thomas Roehr , Michael Jacob
发明人： Thomas Roehr , Michael Jacob
IPC分类号： G11C7/02 , G11C7/08 , G11C7/18 , G11C8/12 , G11C11/22 , H01L27/105
CPC分类号： G11C11/22
摘要： A ferroelectric memory array includes a plurality of memory pages each formed of a plurality of ferroelectric memory cells. The ferroelectric memory cells are supplied by common word lines. Status memory cells are connected to each of the plurality of memory pages, each status memory cell stores the status of the memory page to which it is connected. A plurality of sense amplifiers each receives inputs from a pair of bit lines. Each of the bit lines receives inputs from the ferroelectric memory cells of a plurality of the memory pages. The sense amplifiers write back data into the memory cells and status cells in reversed states following read operations.
摘要翻译：铁电存储器阵列包括由多个铁电存储器单元形成的多个存储器页。铁电存储单元由公用字线提供。状态存储器单元连接到多个存储器页中的每一个，每个状态存储单元存储与其连接的存储器页的状态。多个读出放大器各自接收来自一对位线的输入。每个位线接收来自多个存储器页的铁电存储单元的输入。在读操作之后，感测放大器将数据写入存储单元和状态单元。

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