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1. 发明授权

US07353450B2 Block processing in a maximum a posteriori processor for reduced power consumption 失效
标题翻译：在最大后验处理器中进行块处理，以降低功耗
公开(公告)号：US07353450B2
公开(公告)日：2008-04-01
申请号：US10054687
申请日：2002-01-22
申请人： Thaddeus J. Gabara , Inkyu Lee , Marissa L. Lopez-Vallejo , Syed Mujtaba
发明人： Thaddeus J. Gabara , Inkyu Lee , Marissa L. Lopez-Vallejo , Syed Mujtaba
IPC分类号： H03M13/03
CPC分类号： H04L1/0055 , H03M13/3905 , H03M13/395 , H03M13/3972 , H04L1/0053
摘要： A maximum a posteriori (MAP) processor employs a block processing technique for the MAP algorithm to provide a parallel architecture that allows for multiple word memory read/write processing and voltage scaling of a given circuit implementation. The block processing technique forms a merged trellis with states having modified branch inputs to provide the parallel structure. When block processing occurs, the trellis may be modified to show transitions from the oldest state at time k−N to the present state at time k. For the merged trellis, the number of states remains the same, but each state receives 2N input transitions instead of the two input transitions. Branch metrics associated with the transitions in the merged trellis are cumulative, and are employed for the update process of forward and backward probabilities by the MAP algorithm. During the update process, the read/write operation for an implementation transfers N words of length N for each update operation, but the frequency (and hence, number) of update operations is reduced by a factor of N. Such voltage scaling and multiple word memory read/write may provide reduced power consumption for a given implementation of MAP processor in, for example, a DSP.
摘要翻译：最大后验（MAP）处理器采用用于MAP算法的块处理技术来提供允许给定电路实现的多个字存储器读/写处理和电压缩放的并行架构。块处理技术形成具有修改的分支输入的状态的合并网格以提供并行结构。当块处理发生时，网格可以被修改以显示从时间k-N处的最旧状态到时间k的当前状态的转换。对于合并的网格，状态数量保持不变，但是每个状态都接收两个输入转换，而不是两个输入转换。与合并网格中的转换相关联的分支度量是累积的，并且被MAP算法用于前向和后向概率的更新过程。在更新过程中，对于每个更新操作，实现的读/写操作传送N个长度为N的字，但更新操作的频率（因此，数量）减少了N倍。这种电压缩放和多个字存储器读/写可以为例如DSP中的MAP处理器的给定实现提供降低的功耗。

2. 发明授权

US06317008B1 Clock recovery using an injection tuned resonant circuit 有权
标题翻译：使用注入调谐谐振电路的时钟恢复
公开(公告)号：US06317008B1
公开(公告)日：2001-11-13
申请号：US09236675
申请日：1999-01-26
申请人： Thaddeus J. Gabara
发明人： Thaddeus J. Gabara
IPC分类号： H03B700
CPC分类号： H03L7/0805 , H03J3/20 , H03K3/354 , H03L7/06 , H03L7/24 , H04L7/027
摘要： A tuning signal is injected into an LC tank circuit oscillator, e.g., through an impedance (either reactive, inductive, capacitive and/or resistive) to tune the phase and/or frequency of the LC tank circuit oscillator. A negative resistance is included in parallel with the LC tank circuit oscillator to compensate for losses in the LC tank circuit, and a bias signal is provided to power the operation of the LC tank circuit. Multiple LC tank circuit oscillators may be used to provide stable multiplied or divided frequencies. In another embodiment, the nominal frequency of the LC tank circuit oscillator may be adjusted using a varactor or other voltage-controlled element in the LC tank circuit oscillator under the control of, e.g., the output of a separate PLL loop including another LC tank circuit oscillator. In one application, the injection tuned LC tank circuit forms a clock recovery cell using a clock signal embedded in a NRZ (Non Return to Zero) pseudo-random data stream. The slave oscillator in turn generates a recovered clock signal. In another application, a sub-harmonic clock signal in a 5.6 Gb/s NRZ (Non Return to Zero) 27−1 pseudo-random data stream is used to injection lock a CMOS LC tank circuit to 2.8 GHz. The data stream is de-serialized into two 2.8 Gb/s data streams by a parallel combination of a positive and negative edge flip-flops (FF) clocked with alternate edges of this recovered clock.
摘要翻译：调谐信号例如通过阻抗（无功，电感，电容和/或电阻）被注入LC振荡电路振荡器，以调谐LC振荡电路振荡器的相位和/或频率。 LC电路振荡器并联包含负电阻，以补偿LC电路中的损耗，并提供偏置信号为LC电路的运行提供动力。多个LC振荡电路振荡器可用于提供稳定的倍频或分频。在另一个实施例中，LC振荡电路振荡器的标称频率可以在LC振荡电路振荡器中使用变容二极管或其他电压控制元件进行调节，例如在包括另一个LC振荡电路的单独的PLL回路的输出振荡器在一个应用中，注入调谐的LC槽电路使用嵌入在NRZ（非归零）伪随机数据流中的时钟信号形成时钟恢复单元。从振荡器又产生恢复的时钟信号。在另一个应用中，使用5.6 Gb / s NRZ（非归零）27-1伪随机数据流中的亚谐波时钟信号将CMOS LC槽电路注入到2.8 GHz。数据流通过与这个恢复的时钟的交替边沿时钟的正和负沿触发器（FF）的并联组合被反序列化成两个2.8Gb / s数据流。

3. 发明授权

US5097148A Integrated circuit buffer with improved drive capability 失效
标题翻译：集成电路缓冲器具有改进的驱动能力
公开(公告)号：US5097148A
公开(公告)日：1992-03-17
申请号：US514647
申请日：1990-04-25
申请人： Thaddeus J. Gabara
发明人： Thaddeus J. Gabara
IPC分类号： H03K17/16 , H03K19/003 , H03K19/017 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/00361 , H03K19/01721
摘要： An output buffer provides for additional current sinking or sourcing capability by switching in an additional transistor when the output voltage passes a given level. This allows the output buffer to supply DC current to a load without requiring an excessively large AC drive capability, which could undesirably increase switching noise. In a typical embodiment, an inverter senses when the buffer output voltage reaches its switching threshold (approximately V.sub.DD /2), and turns on the additional transistor after a given delay. For example, a CMOS output buffer driving a TTL load may obtain additional current sinking capability by this technique. On-chip buffers (e.g., bus drivers and clock drivers) can also benefit from this technique.

4. 发明授权

US6157215A Method and apparatus for controlling impedance 失效
标题翻译：用于控制阻抗的方法和装置
公开(公告)号：US6157215A
公开(公告)日：2000-12-05
申请号：US106284
申请日：1998-06-29
申请人： Thaddeus J. Gabara , Stefan A. Siegel
发明人： Thaddeus J. Gabara , Stefan A. Siegel
IPC分类号： H03K19/00 , H03K17/16 , H03K19/003
CPC分类号： H03K19/0005
摘要： A passive resistive element is provided in series with a digital variable impedance to produce a highly linear output impedance for a transmission path over a wide range of operating conditions.
摘要翻译：无源电阻元件与数字可变阻抗串联提供，以在宽范围的工作条件下为传输路径产生高度线性的输出阻抗。

5. 发明授权

US5502328A Bipolar ESD protection for integrated circuits 失效
标题翻译：集成电路的双极ESD保护
公开(公告)号：US5502328A
公开(公告)日：1996-03-26
申请号：US228834
申请日：1994-04-18
申请人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
发明人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
IPC分类号： H01L27/02 , H01L29/00
CPC分类号： H01L27/0259
摘要： CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.
摘要翻译： CMOS集成电路缓冲器通常使用双二极管静电放电（ESD）保护技术。然而，在某些情况下，当在接合板上存在期望的信号电压时，该技术无意中导致二极管中的一个导通，从而限制期望的信号。例如，当未供电设备上的输出缓冲器连接到有源总线时，或者当3伏器件的输入缓冲器接收到5伏特信号时，就会发生这种情况。本发明通过使用连接在接合板和电源总线（例如VSS）之间的双极（例如，pnp）保护晶体管解决了该问题。晶体管的基极通过电阻器连接到接合板，电阻器由于包括分布电容的R-C时间常数而提供时间延迟。时间延迟允许高导通周期，在此期间ESD事件通过双极晶体管传导，从而保护输入或输出缓冲器。

6. 发明授权

US5194765A Digitally controlled element sizing 失效
标题翻译：数字控制元件尺寸
公开(公告)号：US5194765A
公开(公告)日：1993-03-16
申请号：US724560
申请日：1991-06-28
申请人： Alfred E. Dunlop , Thaddeus J. Gabara , Scott C. Knauer
发明人： Alfred E. Dunlop , Thaddeus J. Gabara , Scott C. Knauer
IPC分类号： H03H11/24
CPC分类号： H03H11/245
摘要： Effective control of impedance values in integrated circuit applications is achieved with an integrated circuit transistor whose size is digitally controlled. The digitally controlled size is achieved, for example, with a parallel interconnection of MOS transistors. In one application, the digitally controlled transitor serves as a controlled impedance connected to an output terminal of an integrated circuit. In that application, a number of transistors are enabled with control signals, and the collection of enabled transistors is responsive to the input signal that normally is applied to a conventional transistor. In another application, where the digitally controlled transistor serves as a controlled impedance at the input of a circuit, only the control signals that enable transistors and thereby determine the effective developed impedance are employed. In still another application, the digital control of the transistor's size is employed to control the speed or power consumption of the effective transistor. Such control is exercised to erase the manufacturing variability of the integrated circuit. Alternatively, such control is exercised as part of a feedback control of the operational characteristics of the entire circuit. In the feedback control application, the digital signals that control the transistor's size are obtained from an assessment of the circuit's operation. In the manufacturing variability control application, the digital signals that control the transistor's size are obtained from a measure of the integrated circuit's parameters relative to a reference element.

7. 发明授权

US5040035A MOS devices having improved threshold match 失效
标题翻译： MOS器件具有改进的阈值匹配
公开(公告)号：US5040035A
公开(公告)日：1991-08-13
申请号：US634930
申请日：1990-12-27
申请人： Thaddeus J. Gabara , Peter C. Metz
发明人： Thaddeus J. Gabara , Peter C. Metz
IPC分类号： H01L27/02 , H01L27/088 , H01L27/118
CPC分类号： H01L27/0207 , H01L27/088 , H01L27/11898 , Y10S257/925 , Y10S438/982
摘要： In certain circuits, it is desirable to match the electrical characteristics, (e.g., thresholds), of two (or more) MOS transistors. For example, in an ECL output buffer, a first transistor is a voltage reference, and a second transistor is an output buffer controlled by this voltage reference. However, the orientation of the transistors may affect their electrical characteristics. This may be due to the source/drain ion implantation step that occurs at an angle off the vertical, or other processing effects. The present invention provides symmetrical MOS transistors having characteristics that are independent of orientation. For example, a square gate layout provides both vertical and horizontal current components, thereby obtaining 90 degree rotational symmetry.
摘要翻译：在某些电路中，期望匹配两个（或多个）MOS晶体管的电特性（例如阈值）。例如，在ECL输出缓冲器中，第一晶体管是参考电压，第二晶体管是由该参考电压控制的输出缓冲器。然而，晶体管的取向可能影响其电特性。这可能是由于源/漏离子注入步骤以垂直方向发生的角度或其他处理效应。本发明提供具有独立于取向的特性的对称MOS晶体管。例如，方形栅极布局提供垂直和水平的电流分量，从而获得90度的旋转对称性。

8. 发明授权

US07409659B2 System and method for suppressing crosstalk glitch in digital circuits 失效
标题翻译：抑制数字电路串扰毛刺的系统和方法
公开(公告)号：US07409659B2
公开(公告)日：2008-08-05
申请号：US10988083
申请日：2004-11-12
申请人： Kanad Chakraborty , Thaddeus J. Gabara , Kevin R. Stiles , Bingxiong Xu
发明人： Kanad Chakraborty , Thaddeus J. Gabara , Kevin R. Stiles , Bingxiong Xu
IPC分类号： G06F17/50 , H03K17/16 , H03K19/003 , H01L25/00
CPC分类号： G06F17/505
摘要： A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net is examined to check whether the crosstalk glitch is primarily due to propagated noise from an earlier stage or due to noise injected in the selected victim net. If the crosstalk glitch is propagated from an earlier stage, then a second static latch is inserted before the state in which the first static latch is inserted. Alternatively, another static latch may be inserted in the selected victim net. Cell libraries including a variety of static latch circuit architectures can be designed.
摘要翻译：静态锁存电路用于抑制同步数字集成电路中的串扰毛刺。将静态锁存器插入到所选择的受害网络中，并且如果被选择的受害者网络中引起的串扰毛刺被充分抑制，则检查网络。如果不是，则检查所选择的受害网络以检查串扰毛刺是否主要是由于来自较早阶段的传播噪声或由于在所选择的受害者网络中注入的噪声引起的。如果从较早阶段传播串扰毛刺，则在插入第一静态锁存器的状态之前插入第二静态锁存器。或者，可以在所选择的受害网络中插入另一个静态锁存器。可以设计包括各种静态锁存电路架构的单元库。

9. 发明授权

US07305238B2 Position-based capacity reservation in a mobile wireless system 有权
标题翻译：移动无线系统中基于位置的容量预留
公开(公告)号：US07305238B2
公开(公告)日：2007-12-04
申请号：US10136226
申请日：2002-05-01
申请人： Thaddeus J. Gabara
发明人： Thaddeus J. Gabara
IPC分类号： H04Q7/20
CPC分类号： H04W36/32 , H04W28/26
摘要： A wireless communication network includes position-based capacity reservation of base stations. Using, for example, the Global Positioning System (GPS), a mobile unit may periodically determine its position and communicate its position to base stations as the mobile unit moves through the network. In addition, the capacity needs of the mobile unit's connection may be communicated expressly by the unit or deduced from the connection itself. A network management system receives the position and capacity information of the mobile unit, and then estimates a route of the mobile unit through the network. Such route may be determined either 1) explicitly, given information transmitted by the mobile unit or 2) implicitly, by tracking the direction of movement of the mobile unit through the network. Consequently, the network management system may determine the availability of capacity of base stations along the estimated route through the network. Given this information, the network management system may take one or more of the following actions. First, capacity of each base station along the route may be reserved in anticipation of the mobile unit's arrival into the base station's coverage area. Second, base stations may be selected for handoff along the route and the identity of these base stations communicated to the mobile unit. Third, an alternative route may be communicated to the mobile unit, and that alternative route may include base stations having relatively greater available capacity. Fourth, directions may be provided to the mobile unit to bring the mobile unit closer, in position, to a base station.
摘要翻译：无线通信网络包括基站的基于位置的容量预留。使用例如全球定位系统（GPS），当移动单元移动通过网络时，移动单元可以周期性地确定其位置并将其位置传达给基站。此外，移动单元的连接的容量需求可以由单元明确地传送或从连接本身推断出来。网络管理系统接收移动单元的位置和容量信息，然后通过网络估计移动单元的路由。这样的路由可以明确地确定，给定由移动单元发送的信息，或者2）隐式地通过跟踪移动单元通过网络的移动方向来确定。因此，网络管理系统可以沿着通过网络的估计路由来确定基站的容量的可用性。根据该信息，网络管理系统可以采取以下一个或多个动作。首先，可以预留每个基站沿路由的容量，以预期移动单元到达基站的覆盖区域。第二，可以选择基站沿着路由进行切换，并且将这些基站的身份选择为通信给移动单元。第三，替代路由可以被传送到移动单元，并且该替代路由可以包括具有相对较大可用容量的基站。第四，可以向移动单元提供方向以将移动单元置于更靠近基站的位置。

10. 发明授权

US5675263A Hot-clock adiabatic gate using multiple clock signals with different phases 失效
标题翻译：热时钟绝热门使用多个不同相位的时钟信号
公开(公告)号：US5675263A
公开(公告)日：1997-10-07
申请号：US561547
申请日：1995-11-21
申请人： Thaddeus J. Gabara
发明人： Thaddeus J. Gabara
IPC分类号： H01L21/822 , H01L27/04 , H03K19/00 , H03K19/096
CPC分类号： H03K19/0019 , H03K19/0963
摘要： A hot clock adiabatic gate, using CMOS technology, incorporates an ancillary transistor. The gate is energized by multiple clock signals of different phases to reduce power consumption. The output logic voltage of the gate can reach full-rail voltage by allowing the CMOS technology to discharge via the ancillary transistor. The hot clock adiabatic gate and associated ancillary transistor may be incorporated into various logic circuits, such as an inverter, a memory cell, a NAND gate, and a NOR gate. In one configuration, a CMOS inverter is controlled by four clock signals having four discrete phases. The CMOS inverter optimally includes a CMOS gate transistor pair wherein the semiconductor channels of two ancillary transistors are in series with the semiconductor channels of the CMOS gate transistor pair.
摘要翻译：采用CMOS技术的热时钟绝热门并入了一个辅助晶体管。门由不同相位的多个时钟信号供电，以降低功耗。通过允许CMOS技术通过辅助晶体管放电，栅极的输出逻辑电压可以达到全轨电压。热时钟绝热栅极和相关联的辅助晶体管可以并入到各种逻辑电路中，例如逆变器，存储单元，NAND门和NOR门。在一种配置中，CMOS反相器由具有四个离散相位的四个时钟信号控制。 CMOS反相器最佳地包括CMOS栅极晶体管对，其中两个辅助晶体管的半导体沟道与CMOS栅极晶体管对的半导体沟道串联。

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