专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5304839A Bipolar ESD protection for integrated circuits 失效
标题翻译：集成电路的双极ESD保护
公开(公告)号：US5304839A
公开(公告)日：1994-04-19
申请号：US847438
申请日：1992-03-06
申请人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
发明人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
IPC分类号： H01L27/02 , H01L29/06 , H01L29/02 , H01L29/72 , H01L29/78
CPC分类号： H01L27/0259
摘要： CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.
摘要翻译： CMOS集成电路缓冲器通常使用双二极管静电放电（ESD）保护技术。然而，在某些情况下，当在接合板上存在期望的信号电压时，该技术无意中导致二极管中的一个导通，从而限制期望的信号。例如，当未供电设备上的输出缓冲器连接到有源总线时，或者当3伏器件的输入缓冲器接收到5伏特信号时，就会发生这种情况。本发明通过使用连接在接合板和电源总线（例如VSS）之间的双极（例如，pnp）保护晶体管解决了该问题。晶体管的基极通过电阻器连接到接合板，电阻器由于包括分布电容的R-C时间常数而提供时间延迟。时间延迟允许高导通周期，在此期间ESD事件通过双极晶体管传导，从而保护输入或输出缓冲器。

2. 发明授权

US4736119A Dynamic CMOS current surge control 失效
标题翻译：动态CMOS电流浪涌控制
公开(公告)号：US4736119A
公开(公告)日：1988-04-05
申请号：US11162
申请日：1987-02-04
申请人： Che-Tsung Chen , Kevin D. Kolwicz , Chin-Jen Lin , Won J. Yoon
发明人： Che-Tsung Chen , Kevin D. Kolwicz , Chin-Jen Lin , Won J. Yoon
IPC分类号： G06F1/32 , G06F1/04 , G06F1/30 , G11C19/00 , G11C19/28 , H03K19/00 , H03K19/096 , G06F9/22
CPC分类号： G06F1/30 , H03K19/0008
摘要： Integrated circuits having a large number of transmission gate logic stages have been found to draw a large current surge on power-up. This is due to the floating input node of complementary inverters causing current to flow briefly before clock pulses arrive. The present invention provides a DC voltage on the gates of the pass transistors until the system clock pulses arrive, thereby eliminating the floating node. An optional periodic window may be generated to examine the system clock after power-up, to detect a loss of clock condition.

3. 发明授权

US5502328A Bipolar ESD protection for integrated circuits 失效
标题翻译：集成电路的双极ESD保护
公开(公告)号：US5502328A
公开(公告)日：1996-03-26
申请号：US228834
申请日：1994-04-18
申请人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
发明人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
IPC分类号： H01L27/02 , H01L29/00
CPC分类号： H01L27/0259
摘要： CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.
摘要翻译： CMOS集成电路缓冲器通常使用双二极管静电放电（ESD）保护技术。然而，在某些情况下，当在接合板上存在期望的信号电压时，该技术无意中导致二极管中的一个导通，从而限制期望的信号。例如，当未供电设备上的输出缓冲器连接到有源总线时，或者当3伏器件的输入缓冲器接收到5伏特信号时，就会发生这种情况。本发明通过使用连接在接合板和电源总线（例如VSS）之间的双极（例如，pnp）保护晶体管解决了该问题。晶体管的基极通过电阻器连接到接合板，电阻器由于包括分布电容的R-C时间常数而提供时间延迟。时间延迟允许高导通周期，在此期间ESD事件通过双极晶体管传导，从而保护输入或输出缓冲器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式