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1. 发明授权

US5502328A Bipolar ESD protection for integrated circuits 失效
标题翻译：集成电路的双极ESD保护
公开(公告)号：US5502328A
公开(公告)日：1996-03-26
申请号：US228834
申请日：1994-04-18
申请人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
发明人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
IPC分类号： H01L27/02 , H01L29/00
CPC分类号： H01L27/0259
摘要： CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.
摘要翻译： CMOS集成电路缓冲器通常使用双二极管静电放电（ESD）保护技术。然而，在某些情况下，当在接合板上存在期望的信号电压时，该技术无意中导致二极管中的一个导通，从而限制期望的信号。例如，当未供电设备上的输出缓冲器连接到有源总线时，或者当3伏器件的输入缓冲器接收到5伏特信号时，就会发生这种情况。本发明通过使用连接在接合板和电源总线（例如VSS）之间的双极（例如，pnp）保护晶体管解决了该问题。晶体管的基极通过电阻器连接到接合板，电阻器由于包括分布电容的R-C时间常数而提供时间延迟。时间延迟允许高导通周期，在此期间ESD事件通过双极晶体管传导，从而保护输入或输出缓冲器。

2. 发明授权

US5304839A Bipolar ESD protection for integrated circuits 失效
标题翻译：集成电路的双极ESD保护
公开(公告)号：US5304839A
公开(公告)日：1994-04-19
申请号：US847438
申请日：1992-03-06
申请人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
发明人： Che-Tsung Chen , Thaddeus J. Gabara , Bernard L. Morris , Yehuda Smooha
IPC分类号： H01L27/02 , H01L29/06 , H01L29/02 , H01L29/72 , H01L29/78
CPC分类号： H01L27/0259
摘要： CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.
摘要翻译： CMOS集成电路缓冲器通常使用双二极管静电放电（ESD）保护技术。然而，在某些情况下，当在接合板上存在期望的信号电压时，该技术无意中导致二极管中的一个导通，从而限制期望的信号。例如，当未供电设备上的输出缓冲器连接到有源总线时，或者当3伏器件的输入缓冲器接收到5伏特信号时，就会发生这种情况。本发明通过使用连接在接合板和电源总线（例如VSS）之间的双极（例如，pnp）保护晶体管解决了该问题。晶体管的基极通过电阻器连接到接合板，电阻器由于包括分布电容的R-C时间常数而提供时间延迟。时间延迟允许高导通周期，在此期间ESD事件通过双极晶体管传导，从而保护输入或输出缓冲器。

3. 发明申请

US20080074171A1 Method and Apparatus for Improving Reliability of an Integrated Circuit Having Multiple Power Domains 有权
标题翻译：提高具有多个电源域的集成电路的可靠性的方法和装置
公开(公告)号：US20080074171A1
公开(公告)日：2008-03-27
申请号：US11535198
申请日：2006-09-26
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , H01L27/0251 , H03K19/00315
摘要： An IC having improved reliability includes at least first and second circuit blocks and at least first and second power domains, the first circuit block being connected to the first power domain and the second circuit block being connected to the second power domain. The IC further includes at least one control circuit configured to generate at least first and second control signals. The first control signal is operative to selectively connect the first power domain to a first voltage supply, and the second control signal is operative to selectively connect the second power domain to a second voltage supply. The IC includes at least first and second clamp circuits, the first clamp circuit being connected to the first power domain, the second clamp circuit being connected to the second power domain. Each of the clamp circuits is operative to prevent a voltage on a corresponding power domain from rising above a prescribed voltage level for the corresponding power domain.
摘要翻译：具有改进的可靠性的IC至少包括第一和第二电路块以及至少第一和第二电力域，第一电路块连接到第一电力域，第二电路块连接到第二电力域。 IC还包括被配置为产生至少第一和第二控制信号的至少一个控制电路。第一控制信号用于选择性地将第一功率域连接到第一电压源，并且第二控制信号用于选择性地将第二功率域连接到第二电压源。 IC包括至少第一和第二钳位电路，第一钳位电路连接到第一电源域，第二钳位电路连接到第二电源域。每个钳位电路可操作以防止相应功率域上的电压升高到对应功率域的规定电压电平以上。

4. 发明授权

US07276957B2 Floating well circuit having enhanced latch-up performance 失效
标题翻译：具有增强的闭锁性能的浮动井回路
公开(公告)号：US07276957B2
公开(公告)日：2007-10-02
申请号：US11239840
申请日：2005-09-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Duane J. Loeper , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Duane J. Loeper , Bernard L. Morris , Yehuda Smooha
IPC分类号： H03K
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.
摘要翻译：用于限定其中形成有至少一个金属氧化物半导体器件的浮动阱的电压电位的电路包括感测电路，其可操作以检测浮动阱连接到的节点处的电压，并产生指示性的控制信号节点处的电压是否基本上在电压范围内。电压范围的较低值基本上等于低于电路的第一电源电压的阈值电压。电压范围的较高值基本上等于高于第一电源电压的阈值电压。用于定义浮动阱的电压电位的电路还包括电压发生器电路，其操作以接收控制信号并产生用于响应于控制信号设置阱的电压电位的偏置信号，偏置信号被控制在整个电压范围。

5. 发明申请

US20100232078A1 Electrostatic Discharge Protection Circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US20100232078A1
公开(公告)日：2010-09-16
申请号：US12438460
申请日：2007-10-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H02H9/04
CPC分类号： H01L27/0266
摘要： An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.
摘要翻译： ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器，以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。第二电压供应节点可操作以接收小于第一电压的第二电压。第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值，并且第二电压钳位器用于将第二电压钳位在第二电压在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。

6. 发明授权

US07495873B2 Electrostatic discharge protection in a semiconductor device 有权
标题翻译：半导体器件中的静电放电保护
公开(公告)号：US07495873B2
公开(公告)日：2009-02-24
申请号：US10977881
申请日：2004-10-29
申请人： Dipankar Bhattacharya , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An ESD protection circuit for protecting a circuit from an ESD event occurring between a first voltage supply node and a second voltage supply node associated with the circuit to be protected includes an MOS device having a gate terminal, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal is connected to the first voltage supply node and the second source/drain terminal is connected to the second voltage supply node. The ESD protection circuit further includes a trigger circuit coupled to the gate terminal of the MOS device. The trigger circuit is configured to generate a control signal at the gate terminal of the MOS device for activating the MOS device during the ESD event. At least a portion of the trigger circuit is formed in a floating well which becomes biased to a voltage that is substantially equal to a first voltage when the first voltage is supplied to the first voltage supply node or to a second voltage when the second voltage is applied to the second voltage supply node, whichever voltage is greater.
摘要翻译：一种ESD保护电路，用于保护电路免受在要被保护的电路的第一电压供应节点和第二电压供应节点之间发生的ESD事件的影响，包括具有栅极端子，第一源极/漏极端子和第二电压源的MOS器件源极/漏极端子。第一源极/漏极端子连接到第一电压供应节点，第二源极/漏极端子连接到第二电压供应节点。 ESD保护电路还包括耦合到MOS器件的栅极端子的触发电路。触发电路被配置为在MOS器件的栅极端产生控制信号，以在ESD事件期间激活MOS器件。触发电路的至少一部分形成在浮置阱中，当浮置第二电压为第二电压时，浮置阱被偏置到基本上等于第一电压的电压，或者当第一电压被提供给第一电压供应节点时，施加到第二电压供应节点，无论哪个电压较大。

7. 发明授权

US08089739B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US08089739B2
公开(公告)日：2012-01-03
申请号：US12438460
申请日：2007-10-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H02H3/22 , H02H3/20 , H02H9/04
CPC分类号： H01L27/0266
摘要： An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.
摘要翻译： ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器，以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。第二电压供应节点可操作以接收小于第一电压的第二电压。第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值，并且第二电压钳位器用于将第二电压钳位在第二电压在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。

8. 发明授权

US07145364B2 Self-bypassing voltage level translator circuit 有权
标题翻译：自我旁路电压电平转换电路
公开(公告)号：US07145364B2
公开(公告)日：2006-12-05
申请号：US11065785
申请日：2005-02-25
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H03K19/0175
CPC分类号： H03K3/012 , H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.
摘要翻译：响应于控制信号，电压电平转换器电路可选择性地以至少两种模式之一工作。在第一模式中，电压电平转换器电路用于将提供第一电压的参考第一源的输入信号转换为参考提供第二电压的第二源的输出信号。在第二模式中，电压电平转换器电路用于提供从电压转换器电路的输入到其输出的信号路径，而不转换输入信号。控制信号表示第一电压和第二电压之间的差。

9. 发明授权

US07529071B2 Circuit for selectively bypassing a capacitive element 有权
标题翻译：有选择地绕过电容元件的电路
公开(公告)号：US07529071B2
公开(公告)日：2009-05-05
申请号：US11535719
申请日：2006-09-27
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H02H3/22
CPC分类号： H03K17/063
摘要： A circuit for selectively bypassing a capacitive element includes at least one NMOS device selectively connectable across the capacitive element to be bypassed, and at least first and second PMOS devices. The PMOS devices are selectively connectable together in series across the capacitive element to be bypassed. The NMOS device provides a first bypass path and the first and second PMOS devices collectively provide a second bypass path.
摘要翻译：用于选择性地绕过电容元件的电路包括至少一个可选择地连接在待旁路的电容元件上的NMOS器件，以及至少第一和第二PMOS器件。 PMOS器件可选择性地连接在电容元件上串联在一起以被旁路。 NMOS器件提供第一旁路路径，并且第一和第二PMOS器件共同提供第二旁路路径。

10. 发明授权

US07511550B2 Method and apparatus for improving reliability of an integrated circuit having multiple power domains 有权
标题翻译：用于提高具有多个电力域的集成电路的可靠性的方法和装置
公开(公告)号：US07511550B2
公开(公告)日：2009-03-31
申请号：US11535198
申请日：2006-09-26
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H03K5/08
CPC分类号： H03K19/0016 , H01L27/0251 , H03K19/00315
摘要： An IC having improved reliability includes at least first and second circuit blocks and at least first and second power domains, the first circuit block being connected to the first power domain and the second circuit block being connected to the second power domain. The IC further includes at least one control circuit configured to generate at least first and second control signals. The first control signal is operative to selectively connect the first power domain to a first voltage supply, and the second control signal is operative to selectively connect the second power domain to a second voltage supply. The IC includes at least first and second clamp circuits, the first clamp circuit being connected to the first power domain, the second clamp circuit being connected to the second power domain. Each of the clamp circuits is operative to prevent a voltage on a corresponding power domain from rising above a prescribed voltage level for the corresponding power domain.
摘要翻译：具有改进的可靠性的IC至少包括第一和第二电路块以及至少第一和第二电力域，第一电路块连接到第一电力域，第二电路块连接到第二电力域。 IC还包括被配置为产生至少第一和第二控制信号的至少一个控制电路。第一控制信号用于选择性地将第一功率域连接到第一电压源，并且第二控制信号用于选择性地将第二功率域连接到第二电压源。 IC包括至少第一和第二钳位电路，第一钳位电路连接到第一电源域，第二钳位电路连接到第二电源域。每个钳位电路可操作以防止相应功率域上的电压升高到对应功率域的规定电压电平以上。

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