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1. 发明授权

US5946231A Non-volatile semiconductor memory device 失效
公开(公告)号：US5946231A
公开(公告)日：1999-08-31
申请号：US72664
申请日：1998-05-05
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

2. 发明授权

US6014330A Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US6014330A
公开(公告)日：2000-01-11
申请号：US167969
申请日：1998-10-08
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

3. 发明授权

US5774397A Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state 失效
标题翻译：非易失性半导体存储器件以及将非易失性存储器单元编程到预定状态的方法
公开(公告)号：US5774397A
公开(公告)日：1998-06-30
申请号：US711652
申请日：1996-09-10
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

4. 发明授权

US5555204A Non-volatile semiconductor memory device 失效
标题翻译： Eeprom用于使用隧道电流写入和擦除数据。
公开(公告)号：US5555204A
公开(公告)日：1996-09-10
申请号：US266633
申请日：1994-06-28
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C16/02
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

5. 发明授权

US06188611B1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06188611B1
公开(公告)日：2001-02-13
申请号：US09408441
申请日：1999-09-29
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

6. 发明授权

US5933436A Error correction/detection circuit and semiconductor memory device using the same 失效
标题翻译：误差校正/检测电路及使用其的半导体存储器件
公开(公告)号：US5933436A
公开(公告)日：1999-08-03
申请号：US611818
申请日：1996-03-06
申请人： Toru Tanzawa , Tomoharu Tanaka , Riichiro Shirota , Kazunori Ohuchi
发明人： Toru Tanzawa , Tomoharu Tanaka , Riichiro Shirota , Kazunori Ohuchi
IPC分类号： G06F12/16 , G06F11/10 , H03M13/15 , G11C29/00
CPC分类号： G06F11/1008 , H03M13/151
摘要： An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size calculating circuit for calculating a position and a size of an error from said syndrome; and an error correction circuit for correcting an error for at least information data input in a second cycle on a basis of the position and the size of the error obtained in said error position/size calculating circuit and for outputting at least error-corrected information data.
摘要翻译：一种纠错/检测电路，包括：从第一周期输入的信息数据和检查数据产生校正子的校正子产生电路; 以及误差位置/尺寸计算电路，用于计算所述综合征的误差的位置和尺寸; 以及误差校正电路，用于根据在所述误差位置/尺寸计算电路中获得的误差的位置和尺寸，校正至少在第二周期中输入的信息数据的误差，并且至少输出错误校正的信息数据。

7. 发明授权

US5969988A Voltage multiplier circuit and nonvolatile semiconductor memory device having voltage multiplier 失效
标题翻译：具有电压倍增器电路的电压倍增器电路和非易失性半导体存储器件
公开(公告)号：US5969988A
公开(公告)日：1999-10-19
申请号：US598071
申请日：1996-02-07
申请人： Toru Tanzawa , Tomoharu Tanaka , Hiroshi Nakamura , Yoshiyuki Tanaka
发明人： Toru Tanzawa , Tomoharu Tanaka , Hiroshi Nakamura , Yoshiyuki Tanaka
IPC分类号： G11C17/00 , G05F1/00 , G11C5/14 , G11C16/06 , G11C16/30 , H02M3/07
CPC分类号： G11C5/145 , G11C16/30 , H02M3/073
摘要： A voltage multiplier circuit for raising an input voltage to a predetermined voltage is characterized in that a plurality of multiplier cells for raising an input voltage to be outputted, and a connection switching circuit for switching a connection state of these multiplier cells are provided, and the connection switching circuit connects multiplier cell groups formed by connecting one or a plurality of the multiplier cells, in parallel to an output, and varies the number of the multiplier cells of the multiplier cell groups and that of the multiplier cell groups.
摘要翻译：用于将输入电压升高到预定电压的电压倍增器电路的特征在于，提供用于提高要输出的输入电压的多个乘法器单元和用于切换这些乘法器单元的连接状态的连接切换电路，连接切换电路并联连接一个或多个乘法器单元形成的乘法单元组，并且改变乘法单元组和乘法单元组的乘法单元的数量。

8. 发明授权

US06252798B1 Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse 失效
标题翻译：非易失性半导体存储器件能够控制写入电压脉冲和转换电压脉冲的相互定时
公开(公告)号：US06252798B1
公开(公告)日：2001-06-26
申请号：US09104163
申请日：1998-06-25
申请人： Shinji Satoh , Riichiro Shirota , Toru Tanzawa
发明人： Shinji Satoh , Riichiro Shirota , Toru Tanzawa
IPC分类号： G11C1632
CPC分类号： G11C16/32 , G11C16/0483 , G11C16/08
摘要： A nonvolatile semiconductor memory device comprises a memory cell array having plural electrically erasable memory cells including a gate, a source, a drain, and an electric charge accumulation layer each disposed in a matrix form. A data writing section writes data into memory cells in this memory cell array. A data reading section reads out data in memory cells of the memory cell array. A data erasing section erases data in memory cells of the memory cell array. A control section controls, when applying a first signal to the gate in a specified memory inhibited of writing and applying a second signal to a node capacitively coupled to at least one of source and drain, in writing data into the memory cells, so that the second signal may fall later than the first signal.
摘要翻译：非易失性半导体存储器件包括具有多个电可擦除存储单元的存储单元阵列，每个电可擦除存储单元包括以矩阵形式设置的栅极，源极，漏极和电荷累积层。数据写入部分将数据写入该存储单元阵列中的存储单元。数据读取部读出存储单元阵列的存储单元中的数据。数据擦除部分擦除存储单元阵列的存储单元中的数据。控制部分在将指定的存储器中的门施加禁止写入的第一信号并且将第二信号施加到电容耦合到源极和漏极中的至少一个的节点时控制将数据写入存储器单元中，从而使得第二信号可能晚于第一信号。

9. 发明授权

US07649780B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07649780B2
公开(公告)日：2010-01-19
申请号：US12040457
申请日：2008-02-29
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Toru Tanzawa
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C16/26 , G11C2211/5642
摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.
摘要翻译：半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

10. 发明授权

US07509566B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US07509566B2
公开(公告)日：2009-03-24
申请号：US11747225
申请日：2007-05-10
申请人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
发明人： Tomoharu Tanaka , Noboru Shibata , Toru Tanzawa
IPC分类号： H03M13/00 , G11C29/00 , G11C11/34
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2029/0411 , G11C2207/104
摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.
摘要翻译：闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路，和写电路。命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。误差校正电路由写数据输入指令信号激活，以与写使能信号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

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