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1. 发明授权

US06252798B1 Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse 失效
标题翻译：非易失性半导体存储器件能够控制写入电压脉冲和转换电压脉冲的相互定时
公开(公告)号：US06252798B1
公开(公告)日：2001-06-26
申请号：US09104163
申请日：1998-06-25
申请人： Shinji Satoh , Riichiro Shirota , Toru Tanzawa
发明人： Shinji Satoh , Riichiro Shirota , Toru Tanzawa
IPC分类号： G11C1632
CPC分类号： G11C16/32 , G11C16/0483 , G11C16/08
摘要： A nonvolatile semiconductor memory device comprises a memory cell array having plural electrically erasable memory cells including a gate, a source, a drain, and an electric charge accumulation layer each disposed in a matrix form. A data writing section writes data into memory cells in this memory cell array. A data reading section reads out data in memory cells of the memory cell array. A data erasing section erases data in memory cells of the memory cell array. A control section controls, when applying a first signal to the gate in a specified memory inhibited of writing and applying a second signal to a node capacitively coupled to at least one of source and drain, in writing data into the memory cells, so that the second signal may fall later than the first signal.
摘要翻译：非易失性半导体存储器件包括具有多个电可擦除存储单元的存储单元阵列，每个电可擦除存储单元包括以矩阵形式设置的栅极，源极，漏极和电荷累积层。数据写入部分将数据写入该存储单元阵列中的存储单元。数据读取部读出存储单元阵列的存储单元中的数据。数据擦除部分擦除存储单元阵列的存储单元中的数据。控制部分在将指定的存储器中的门施加禁止写入的第一信号并且将第二信号施加到电容耦合到源极和漏极中的至少一个的节点时控制将数据写入存储器单元中，从而使得第二信号可能晚于第一信号。

2. 发明授权

US6117729A Nonvolatile semiconductor storage device and its manufacturing method 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US6117729A
公开(公告)日：2000-09-12
申请号：US97152
申请日：1998-06-12
申请人： Hirohisa Iizuka , Shinji Satoh , Riichiro Shirota
发明人： Hirohisa Iizuka , Shinji Satoh , Riichiro Shirota
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.
摘要翻译：用于隔离具有与半导体衬底10相同的导电类型的位线接触的高浓度杂质区24形成在半导体衬底10中的场氧化物膜12下的位于选择晶体管的各漏极区之间的位置多个NAND存储器单元。用于隔离位线触点的高浓度杂质区24是通过将杂质注入到半导体衬底10中的狭缝20a，20b以第一个方式制造的共同步骤制成用于隔离存储晶体管的高浓度杂质区26 高浓度杂质区24防止位线触点42a之间的穿通现象，并提高位线触点42a之间的电压电阻率。

3. 发明授权

US06314026B1 Nonvolatile semiconductor device using local self boost technique 有权
标题翻译：非易失性半导体器件采用局部自增强技术
公开(公告)号：US06314026B1
公开(公告)日：2001-11-06
申请号：US09500315
申请日：2000-02-08
申请人： Shinji Satoh , Fumitaka Arai , Riichiro Shirota
发明人： Shinji Satoh , Fumitaka Arai , Riichiro Shirota
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/16 , G11C16/26 , G11C16/3404 , G11C16/3409
摘要： With a local self boost (LSB) technique, the distribution of threshold voltages after data erase is set toward a higher side and the distribution width is narrowed sufficiently within the range in which cell erase states can be read. To this end, block write is carried out on a memory cell array. Next, setting a predetermined voltage as a start voltage, soft erase is carried out for each block. After carrying out erase verification read, the threshold voltages of the cells are compared with a determination reference value. As a result of this comparison, if the threshold voltages of the cells do not reach the determination reference value, soft erase is repeated. In that case, the predetermined voltage during the soft erase is changed from the start voltage. When the threshold voltages of all the cells have reached the determination reference value, the soft erase is ended.
摘要翻译：利用本地自升压（LSB）技术，将数据擦除后的阈值电压分配设置为较高一侧，并且在可读取单元擦除状态的范围内，分布宽度变窄。为此，在存储单元阵列上执行块写入。接下来，将预定电压设置为起始电压，对每个块执行软擦除。在执行擦除验证读取之后，将单元的阈值电压与确定基准值进行比较。作为该比较的结果，如果单元的阈值电压未达到确定基准值，则重复软擦除。在这种情况下，软擦除期间的预定电压从起始电压改变。当所有单元的阈值电压都达到确定基准值时，软擦除结束。

4. 发明授权

US06493265B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06493265B2
公开(公告)日：2002-12-10
申请号：US10114960
申请日：2002-04-02
申请人： Shinji Satoh , Fumitaka Arai , Riichiro Shirota
发明人： Shinji Satoh , Fumitaka Arai , Riichiro Shirota
IPC分类号： G11C1606
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/16 , G11C16/26 , G11C16/3404 , G11C16/3409
摘要： A method of determining multi-bit data in a multi-level memory. The method includes setting a source potential of a memory cell to a first source potential, setting a gate potential thereof to a first read-out potential, and determining if bit data of a first digit of multi-bit data is “0” or “1”. Also, the method includes setting the source potential of the memory cell to the first source potential and setting the gate potential thereof to a second read-out potential that is different from the first read-out potential when the bit data of the first digit is “0”, and determining if bit data of a second digit of the multi-bit data is “0” or “1”. In addition the method includes setting the source potential of the memory cell to a second source potential different from the first source potential and setting the gate potential thereof to the second read-out potential when the bit data of the first digit is “1”, and determining if bit data of the second digit of the multi-bit data is “0” or “1”.
摘要翻译：一种在多级存储器中确定多位数据的方法。该方法包括将存储器单元的源极电位设置为第一源极电位，将其栅极电位设置为第一读出电位，以及确定多位数据的第一位数据的位数据是否为“0”或“ 1“。此外，该方法包括将存储单元的源极电位设置为第一源极电位，并且当第一数字位的位数据为第一数据位时，将其栅极电位设置为与第一读出电位不同的第二读出电位 “0”，并且确定多位数据的第二数位的位数据是“0”还是“1”。此外，该方法包括：当第一数位的位数据为“1”时，将存储单元的源极电位设置为不同于第一源电位的第二源极电位，并将其栅极电位设置为第二读出电位，以及确定所述多位数据的第二数位的位数据是否为“0”或“1”。

5. 发明授权

US06288942B1 Nonvolatile semiconductor storage device and its manufacturing method 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06288942B1
公开(公告)日：2001-09-11
申请号：US09632626
申请日：2000-08-04
申请人： Hirohisa Iizuka , Shinji Satoh , Riichiro Shirota
发明人： Hirohisa Iizuka , Shinji Satoh , Riichiro Shirota
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.
摘要翻译：用于隔离具有与半导体衬底10相同的导电类型的位线接触的高浓度杂质区24形成在半导体衬底10中的场氧化物膜12下的位于选择晶体管的各漏极区之间的位置多个NAND存储器单元。用于隔离位线触点的高浓度杂质区24是通过将杂质注入到半导体衬底10中的狭缝20a，20b以第一个方式制造的共同步骤制成用于隔离存储晶体管的高浓度杂质区26 高浓度杂质区24防止位线触点42a之间的穿通现象，并提高位线触点42a之间的电压电阻率。

6. 发明授权

US06459612B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06459612B2
公开(公告)日：2002-10-01
申请号：US09953687
申请日：2001-09-14
申请人： Shinji Satoh , Fumitaka Arai , Riichiro Shirota
发明人： Shinji Satoh , Fumitaka Arai , Riichiro Shirota
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/16 , G11C16/26 , G11C16/3404 , G11C16/3409
摘要： With a local self boost (LSB) technique, the distribution, of threshold voltages after data erase is set toward a higher side and the distribution width is narrowed sufficiently within the range in which cell erase states can be read. To this end, block write is carried out on a memory cell array. Next, setting a predetermined voltage as a start voltage, soft erase is carried out for each block. After carrying out erase verification read, the threshold voltages of the cells are compared with a determination reference value. As a result of this comparison, if the threshold voltages of the cells do not reach the determination reference value, soft erase is repeated. In that case, the predetermined voltage during the soft erase is changed from the start voltage. When the threshold voltages of all the cells have reached the determination reference value, the soft erase is ended.
摘要翻译：利用局部自升压（LSB）技术，将数据擦除后的阈值电压的分布设置为较高一侧，并且分布宽度在可读取单元擦除状态的范围内充分变窄。为此，在存储单元阵列上执行块写入。接下来，将预定电压设置为起始电压，对每个块执行软擦除。在执行擦除验证读取之后，将单元的阈值电压与确定基准值进行比较。作为该比较的结果，如果单元的阈值电压未达到确定基准值，则重复软擦除。在这种情况下，软擦除期间的预定电压从起始电压改变。当所有单元的阈值电压都达到确定基准值时，软擦除结束。

7. 发明授权

US06310374B1 Nonvolatile semiconductor memory device having extracting electrode 失效
标题翻译：具有提取电极的非易失性半导体存储器件
公开(公告)号：US06310374B1
公开(公告)日：2001-10-30
申请号：US09217089
申请日：1998-12-21
申请人： Shinji Satoh , Riichiro Shirota , Seiichi Aritome
发明人： Shinji Satoh , Riichiro Shirota , Seiichi Aritome
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： This invention is a nonvolatile semiconductor memory device including an electrically rewritable memory cell having a gate, source, drain, and charge storage layer, an extracting electrode electrically connected to at least one of the source and drain of the memory cell, and a counter electrode essentially capacitively coupled with the extracting electrode.
摘要翻译：本发明是一种非易失性半导体存储器件，包括具有栅极，源极，漏极和电荷存储层的电可重写存储单元，与存储单元的源极和漏极中的至少一个电连接的提取电极和对电极基本上与提取电极电容耦合。

8. 发明授权

US06917345B2 Small antenna and manufacturing method thereof 失效
标题翻译：小型天线及其制造方法
公开(公告)号：US06917345B2
公开(公告)日：2005-07-12
申请号：US10034847
申请日：2001-12-21
申请人： Hiroki Hamada , Yoshikazu Kamei , Masayuki Ishiwa , Isao Tomomatsu , Takahiro Ueno , Shinji Satoh
发明人： Hiroki Hamada , Yoshikazu Kamei , Masayuki Ishiwa , Isao Tomomatsu , Takahiro Ueno , Shinji Satoh
IPC分类号： H01Q13/08 , B29C45/16 , H01Q1/24 , H01Q1/38
CPC分类号： B29C45/1671 , H01Q1/243 , H01Q1/38
摘要： A small antenna comprises an antenna conductor, and a dielectric chip formed at surroundings of the antenna conductor by a plurality of resin moldings.
摘要翻译：小型天线包括天线导体和通过多个树脂模制件形成在天线导体的周围的电介质芯片。

9. 发明授权

US06894646B2 Line-shaped antenna 失效
标题翻译：线形天线
公开(公告)号：US06894646B2
公开(公告)日：2005-05-17
申请号：US10150138
申请日：2002-05-15
申请人： Takanori Washiro , Isao Tomomatsu , Hiroki Hamada , Shinji Satoh
发明人： Takanori Washiro , Isao Tomomatsu , Hiroki Hamada , Shinji Satoh
IPC分类号： H01Q11/16 , H01Q1/38
CPC分类号： H01Q1/38 , Y10T29/49016
摘要： A line-shaped comprises an antenna element in which a strip-shaped conductor is bent in a width direction of a strip, and a chamfered portion is provided on an outer edge of a bent portion of the strip-shaped conductor.
摘要翻译：线状包括天线元件，其中带状导体沿条带的宽度方向弯曲，并且倒角部分设置在条形导体的弯曲部分的外边缘上。

10. 发明授权

US06724347B2 Chip antenna and method of manufacturing the same 失效
标题翻译：芯片天线及其制造方法
公开(公告)号：US06724347B2
公开(公告)日：2004-04-20
申请号：US10178328
申请日：2002-06-20
申请人： Isao Tomomatsu , Takahiro Ueno , Mitsuo Yoshino , Shinji Satoh , Hiroki Hamada
发明人： Isao Tomomatsu , Takahiro Ueno , Mitsuo Yoshino , Shinji Satoh , Hiroki Hamada
IPC分类号： H01Q138
CPC分类号： H01Q1/2283 , B29C45/0025 , B29C45/14639 , B29L2031/3456 , H01Q1/22 , H01Q1/38 , H01Q1/40 , H01Q9/40 , H01Q9/42 , H01Q11/04
摘要： Of margins of a resin molding with an antenna element buried therein which lie around the antenna element, a margin on that side of the resin molding where a gate mark remains is made larger than margins on other sides where there is no gate mark. Particularly, when the antenna element has a line antenna portion and a capacitance-adding portion provided at a distal end of the line antenna portion, the resin molding is injection-molded in such a way that a gate mark can be formed on that side where the capacitance-adding portion is located. Those portions of the resin molding where the terminal portions are led out are dented from levels of portions around those portions. This provides a chip antenna which has a simple structure with a high mechanical strength and does not prevent separation or cracking from occurring in the resin molding in which the antenna element is buried and a method of manufacturing the chip antenna.
摘要翻译：在埋设在天线元件周围的天线元件的树脂模制品的边缘处，留下栅极标记的树脂模制品侧的边缘大于没有栅极标记的另一侧的边缘。特别地，当天线元件具有线天线部分和设置在线天线部分的远端处的电容增加部分时，树脂模制件以这样的方式被注射成型，即可以在那一侧形成栅极标记电容添加部分被定位。端子部分被引出的树脂模塑件的那些部分由这些部分周围的部分的凹陷凹陷。这提供了具有机械强度高的简单结构的芯片天线，并且不防止在埋设天线元件的树脂模制件中发生分离或破裂以及制造芯片天线的方法。

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