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1. 发明授权

US07167520B2 Transcoder 失效
标题翻译：转码器
公开(公告)号：US07167520B2
公开(公告)日：2007-01-23
申请号：US10686237
申请日：2003-10-15
申请人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
发明人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
IPC分类号： H04B1/66
CPC分类号： G06T3/40 , H04N19/16 , H04N19/40 , H04N19/42 , H04N19/59 , H04N19/61
摘要： A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.
摘要翻译：一种用于调整视频数据大小并将调整大小的视频数据输出到再现设备的代码转换器。再现装置通过重复显示周期和非显示周期交替地再现调整大小的视频数据。代码转换器包括：调整大小的视频数据的调整大小; 以及控制单元，其使所述调整大小单元将所述视频数据的大小调整为具有第一分辨率的第一视频数据，使得所述再现设备在每个显示周期期间显示一个图像，并且使得调整大小单元在调整大小将视频数据提供给第一视频数据，将视频数据转换为具有低于第一分辨率的第二分辨率的第二视频数据。

2. 发明授权

US07007138B2 Apparatus, method, and computer program for resource request arbitration 有权
标题翻译：用于资源请求仲裁的装置，方法和计算机程序
公开(公告)号：US07007138B2
公开(公告)日：2006-02-28
申请号：US10413758
申请日：2003-04-15
申请人： Tetsuji Mochida , Kosuke Yoshioka , Tokuzo Kiyohara
发明人： Tetsuji Mochida , Kosuke Yoshioka , Tokuzo Kiyohara
IPC分类号： G06F13/16
CPC分类号： G06F13/1642
摘要： In a resource request arbitration apparatus according to the present invention, a request masking unit masks a memory access request REQ that is issued by a resource requesting device at over a minimum frequency needed for the resource requesting device, and an arbitrating unit acknowledges one of the memory access requests RREQ that are not suspended by the request masking unit, based on a predetermined static order of priority. With this resource request arbitration apparatus, the arbitrating unit do not have to concern anything other than the predetermined priority order among the memory access requesting units, and an easy and plain arbitration system based on the static priority order ensures the minimum frequency for acknowledging the resource requests that each memory access requesting unit needs.
摘要翻译：在根据本发明的资源请求仲裁设备中，请求屏蔽单元以资源请求设备所需的最小频率对由资源请求设备发出的存储器访问请求REQ进行掩码，并且仲裁单元确认基于优先级的预定静态顺序，请求屏蔽单元未暂停的存储器访问请求RREQ。在该资源请求仲裁装置中，仲裁单元不需要涉及存储器访问请求单元之间的预定优先级顺序以外的任何其他事项，并且基于静态优先级顺序的容易且简单的仲裁系统确保用于确认资源的最小频率请求每个存储器访问请求单元需要。

3. 发明申请

US20050238095A1 Transcoder 失效
标题翻译：转码器
公开(公告)号：US20050238095A1
公开(公告)日：2005-10-27
申请号：US10686237
申请日：2003-10-15
申请人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
发明人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
IPC分类号： G06T3/40 , H04N7/12 , H04N7/26 , H04N7/46 , H04N7/50
CPC分类号： G06T3/40 , H04N19/16 , H04N19/40 , H04N19/42 , H04N19/59 , H04N19/61
摘要： A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.
摘要翻译：一种用于调整视频数据大小并将调整大小的视频数据输出到再现设备的代码转换器。再现装置通过重复显示周期和非显示周期交替地再现调整大小的视频数据。代码转换器包括：调整大小的视频数据的调整大小; 以及控制单元，其使所述调整大小单元将所述视频数据的大小调整为具有第一分辨率的第一视频数据，使得所述再现设备在每个显示周期期间显示一个图像，并且使得调整大小单元在调整大小将视频数据提供给第一视频数据，将视频数据转换为具有低于第一分辨率的第二分辨率的第二视频数据。

4. 发明授权

US6075899A Image decoder and image memory overcoming various kinds of delaying factors caused by hardware specifications specific to image memory by improving storing system and reading-out system 失效
标题翻译：图像解码器和图像存储器通过改进存储系统和读出系统来克服由图像存储器特有的硬件规格引起的各种延迟因素
公开(公告)号：US6075899A
公开(公告)日：2000-06-13
申请号：US66308
申请日：1998-03-27
申请人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
发明人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
IPC分类号： H04N5/907 , H04N9/64 , H04N19/00 , H04N19/423 , H04N19/426 , H04N19/44 , H04N19/46 , H04N19/503 , H04N19/59 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/85 , H04N19/91 , G06K9/46
CPC分类号： H04N5/907 , H04N19/42 , H04N19/423 , H04N19/61 , H04N9/64
摘要： An image memory stores a one-screen image by dividing the one-screen image into a plurality of image blocks which are each m pixels wide by n pixels high. The image memory has an array-like storage region storing s*t first chrominance components that compose one image block and s*t second chrominance components that compose the same image block in serial areas between a start area specified by a row address and a first column address and an end area specified by the same row address and a second column address (see FIG. 10). The storage region also stores m*n luminance components that compose the same image block in serial areas between a different start area specified by a different row address and a third column address and an end area are specified by the different row address and a fourth column address.
摘要翻译： PCT No.PCT / JP97 / 02995 Sec。 371日期：1998年4月27日 102（e）日期1998年4月27日PCT 1997年8月29日PCT公布。第WO98 / 09444号公报日期1998年3月5日图像存储器通过将单屏图像分成多个像素宽×高n个像素的图像块来存储单屏图像。图像存储器具有存储s * t个第一色度分量的阵列状存储区域，其构成一个图像块和s * t个第二色度分量，其在由行地址指定的起始区域和第一个列地址和由相同行地址和第二列地址指定的结束区域（参见图10）。存储区域还存储在由不同行地址指定的不同起始区域和第三列地址之间的串行区域中构成相同图像块的m * n个亮度分量，并且结束区域由不同的行地址和第四列地址。

5. 发明申请

US20050018914A1 Pixel processing circuit, decoding apparatus, and pixel processing method 审中-公开
标题翻译：像素处理电路，解码装置和像素处理方法
公开(公告)号：US20050018914A1
公开(公告)日：2005-01-27
申请号：US10865416
申请日：2004-06-10
申请人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
发明人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
IPC分类号： H04N19/50 , G06K9/36 , G06T1/20 , H04N19/105 , H04N19/20 , H04N19/21 , H04N19/423 , H04N19/59
CPC分类号： G06T1/20 , G06T9/20 , H04N19/20 , H04N19/42 , H04N19/44 , H04N19/61
摘要： The invention provides a circuit used in a padding and other processes necessary for coding of objects, and performs at high speed pixel processing to generate pixel values to be assigned to cells, using pixel values in a reference area, which includes cells with and without a pixel value. A cell address outputting unit (i) obtains cell addresses indicating positions of a predetermined number of cells serially arranged and binary signals expressing whether those cells each have a pixel value, and (ii) selects, for each cell, two of the obtained cell addresses corresponding to a part of binary signals each expressing that a cell has a pixel value, and outputs the selected cell addresses. A reading unit reads pixel values of the cells at the outputted cell addresses. An operating unit calculates the average of the two read pixel values and outputs the average as a pixel value.
摘要翻译：本发明提供了一种用于填充和其他对象编码所需的处理的电路，并使用参考区域中的像素值在高速像素处理中执行以分配给单元的像素值，该电路包括具有和不具有像素值。单元地址输出单元（i）获得指示串行排列的预定数量的单元的位置的单元地址，以及表示这些单元是否具有像素值的二进制信号，以及（ii）为每个单元选择两个获得的单元地址对应于每个表示单元具有像素值的二进制信号的一部分，并输出所选择的单元地址。读取单元读取输出的单元地址处的单元的像素值。操作单元计算两个读取像素值的平均值，并将该平均值作为像素值输出。

6. 发明授权

US07228064B2 Image decoding apparatus, recording medium which computer can read from, and program which computer can read 失效
标题翻译：图像解码装置，计算机可读取的记录介质，以及计算机可读取的程序
公开(公告)号：US07228064B2
公开(公告)日：2007-06-05
申请号：US10211716
申请日：2002-08-02
申请人： Yoshiyuki Wada , Makoto Hirai , Tokuzo Kiyohara , Kosuke Yoshioka , Hideshi Nishida , Yukiharu Ieda
发明人： Yoshiyuki Wada , Makoto Hirai , Tokuzo Kiyohara , Kosuke Yoshioka , Hideshi Nishida , Yukiharu Ieda
IPC分类号： H04N7/26 , H03N7/40
CPC分类号： H04N9/7921 , H04N5/78266 , H04N9/8042 , H04N9/8047 , H04N19/42
摘要： The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.
摘要翻译：本发明提供一种图像解码装置，其实现从由第一DCT块和MR组成的固定长度单元取出MR（宏块余数）的加速处理，而不增加成本。安装处理器3输出构成SB（同步块）的多个固定长度单元中的一个。首先，从固定长度单位的开始到包括在固定长度单位中的EOB（块末尾）的长度进行计算。然后将计算出的长度用作取出MR的偏移量。然后，包括在MR中的第二DCT块的结束部分与第二DCT块的对应开始部分组合，以便获得完整的第二DCT块。完整的第二DCT块被输出到可变长度码解码器13。

7. 发明授权

US07079583B2 Media processing apparatus which operates at high efficiency 有权
公开(公告)号：US07079583B2
公开(公告)日：2006-07-18
申请号：US10007248
申请日：2001-10-24
申请人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
发明人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
IPC分类号： H04N7/12
CPC分类号： H04N19/90 , H04N5/4401 , H04N21/426 , H04N21/42607 , H04N21/42653 , H04N21/42692 , H04N21/4302 , H04N21/4341
摘要： A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing. Accordingly, the input/output processing means and the decode processing means are respectively charged with the asynchronous processing and the decode processing, and the input/output processing means and the decode processing means operate in parallel as in pipeline processing. As a result, the decode processing means can be devoted to the decode processing, regardless of asynchronous processing. Accordingly, processes including input processing of stream data, decode processing of the inputted data, and output processing of decoded data are executed efficiently.

8. 发明授权

US06987811B2 Image processor and image processing method 有权
标题翻译：图像处理器和图像处理方法
公开(公告)号：US06987811B2
公开(公告)日：2006-01-17
申请号：US10048360
申请日：2001-05-31
申请人： Takaharu Tanaka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
发明人： Takaharu Tanaka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
IPC分类号： H04N7/12
CPC分类号： H03M7/40 , H04N19/129 , H04N19/132 , H04N19/18 , H04N19/42 , H04N19/60
摘要： The speed of decoding processing for variable-length coded image data is improved. The image processor includes a variable-length decoding unit for variable-length decoding input data and outputting a pair of the run length of zero coefficients and a non-zero coefficient; an inverse quantization unit for subjecting the non-zero coefficient to inverse quantization and obtaining inverse quantized data to be output; an address setting unit for carrying out inverse scanning, obtaining an address for storing the inverse quantized data on the basis of the run length of zero coefficients and specifying the address in the data storage unit; a write information storage unit for setting a write flag in an address thereof corresponding to the specified address; and a data reading unit for reading data from the data storage unit, and on the basis of information stored in the write information storage unit, directly outputting data from the address specified by the address setting unit while substituting a predetermined value for data from an address other than the specified address to output the substituted value.
摘要翻译：提高了可变长度编码图像数据的解码处理速度。图像处理器包括：可变长度解码单元，用于对输入数据进行可变长度解码并输出一对零系数的游程长度和非零系数; 逆量化单元，用于对非零系数进行逆量化，并获得要被输出的反量化数据; 地址设定单元，用于执行反向扫描，基于零系数的游程长度获得用于存储逆量化数据的地址，并指定数据存储单元中的地址; 写入信息存储单元，用于在对应于指定地址的地址中设置写入标志; 以及数据读取单元，用于从数据存储单元读取数据，并且基于存储在写入信息存储单元中的信息，直接从地址设置单元指定的地址输出数据，同时从地址替换预定值的数据除了指定的地址以输出替代值。

9. 发明授权

US06310921B1 Media processing apparatus which operates at high efficiency 失效
标题翻译：以高效率运行的媒体处理装置
公开(公告)号：US06310921B1
公开(公告)日：2001-10-30
申请号：US09055583
申请日：1998-04-06
申请人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
发明人： Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara , Kozo Kimura
IPC分类号： H04N712
CPC分类号： H04N19/90 , H04N5/4401 , H04N21/426 , H04N21/42607 , H04N21/42653 , H04N21/42692 , H04N21/4302 , H04N21/4341
摘要： A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing. Accordingly, the input/output processing means and the decode processing means are respectively charged with the asynchronous processing and the decode processing, and the input/output processing means and the decode processing means operate in parallel as in pipeline processing. As a result, the decode processing means can be devoted to the decode processing, regardless of asynchronous processing. Accordingly, processes including input processing of stream data, decode processing of the inputted data, and output processing of decoded data are executed efficiently.
摘要翻译：媒体处理装置由用于执行由于外部因素而异步发生的输入/输出处理的I / O处理单元和用于执行主要用于解码存储在存储器中的数据流的解码处理的解码处理单元输入/输出处理。输入/输出处理包括接收异步输入的数据流，将输入的数据流存储在存储器中，并将数据流从存储器提供给解码处理单元。解码处理单元由主要对数据流执行条件判断的顺序处理单元和与压缩视频数据的标题分析相一致的压缩视频数据执行解码处理的例程处理单元构成，与顺序处理并行。因此，输入/输出处理装置和解码处理装置分别充有异步处理和解码处理，并且输入/输出处理装置和解码处理装置如在流水线处理中并行操作。结果，无论异步处理如何，解码处理装置都可以用于解码处理。因此，有效地执行包括流数据的输入处理，输入数据的解码处理和解码数据的输出处理的处理。

10. 发明授权

US06470376B1 Processor capable of efficiently executing many asynchronous event tasks 失效
标题翻译：处理器能够有效地执行许多异步事件任务
公开(公告)号：US06470376B1
公开(公告)日：2002-10-22
申请号：US09034198
申请日：1998-03-03
申请人： Takaharu Tanaka , Kiyoshi Maenobu , Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara
发明人： Takaharu Tanaka , Kiyoshi Maenobu , Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara
IPC分类号： G06F900
CPC分类号： G06F9/4881 , G06F9/30087 , G06F9/3009 , G06F9/3851 , H04N19/42 , H04N19/61
摘要： The counter 52 is set with an initial value of “1” and is a counter with a maximum value of “4”. This counter 52 increments the count value held by the flip-flop 51 in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1,2,3,4. This clock signal is also used by the instruction decode control unit 11 to control the execution of instructions, with the counting by the counter 52 being performed once for each instruction execution performed by the instruction decode control unit 11. The comparator 54 compares the count value counted by the counter 52 with the maximum value “4”, and when the values match, sets the task switching signal chg_task_ex at a “High” value, so that the processing switches to the execution of the next task.
摘要翻译：计数器52被设置为初始值“1”，并且是具有最大值“4”的计数器。该计数器52与时钟信号同步地增加由触发器51保持的计数值，使得计数值如进展1,2,3,4,1,2,3,4所示变化。指令解码控制单元11还使用该时钟信号来控制指令的执行，计数器52对由指令解码控制单元11进行的每个指令执行一次执行一次计数。比较器54将计数值由具有最大值“4”的计数器52计数，并且当该值匹配时，将任务切换信号chg_task_ex设置为“高”值，使得处理切换到下一任务的执行。

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