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1. 发明授权

US06987811B2 Image processor and image processing method 有权
标题翻译：图像处理器和图像处理方法
公开(公告)号：US06987811B2
公开(公告)日：2006-01-17
申请号：US10048360
申请日：2001-05-31
申请人： Takaharu Tanaka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
发明人： Takaharu Tanaka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
IPC分类号： H04N7/12
CPC分类号： H03M7/40 , H04N19/129 , H04N19/132 , H04N19/18 , H04N19/42 , H04N19/60
摘要： The speed of decoding processing for variable-length coded image data is improved. The image processor includes a variable-length decoding unit for variable-length decoding input data and outputting a pair of the run length of zero coefficients and a non-zero coefficient; an inverse quantization unit for subjecting the non-zero coefficient to inverse quantization and obtaining inverse quantized data to be output; an address setting unit for carrying out inverse scanning, obtaining an address for storing the inverse quantized data on the basis of the run length of zero coefficients and specifying the address in the data storage unit; a write information storage unit for setting a write flag in an address thereof corresponding to the specified address; and a data reading unit for reading data from the data storage unit, and on the basis of information stored in the write information storage unit, directly outputting data from the address specified by the address setting unit while substituting a predetermined value for data from an address other than the specified address to output the substituted value.
摘要翻译：提高了可变长度编码图像数据的解码处理速度。图像处理器包括：可变长度解码单元，用于对输入数据进行可变长度解码并输出一对零系数的游程长度和非零系数; 逆量化单元，用于对非零系数进行逆量化，并获得要被输出的反量化数据; 地址设定单元，用于执行反向扫描，基于零系数的游程长度获得用于存储逆量化数据的地址，并指定数据存储单元中的地址; 写入信息存储单元，用于在对应于指定地址的地址中设置写入标志; 以及数据读取单元，用于从数据存储单元读取数据，并且基于存储在写入信息存储单元中的信息，直接从地址设置单元指定的地址输出数据，同时从地址替换预定值的数据除了指定的地址以输出替代值。

2. 发明授权

US07167520B2 Transcoder 失效
标题翻译：转码器
公开(公告)号：US07167520B2
公开(公告)日：2007-01-23
申请号：US10686237
申请日：2003-10-15
申请人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
发明人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
IPC分类号： H04B1/66
CPC分类号： G06T3/40 , H04N19/16 , H04N19/40 , H04N19/42 , H04N19/59 , H04N19/61
摘要： A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.
摘要翻译：一种用于调整视频数据大小并将调整大小的视频数据输出到再现设备的代码转换器。再现装置通过重复显示周期和非显示周期交替地再现调整大小的视频数据。代码转换器包括：调整大小的视频数据的调整大小; 以及控制单元，其使所述调整大小单元将所述视频数据的大小调整为具有第一分辨率的第一视频数据，使得所述再现设备在每个显示周期期间显示一个图像，并且使得调整大小单元在调整大小将视频数据提供给第一视频数据，将视频数据转换为具有低于第一分辨率的第二分辨率的第二视频数据。

3. 发明授权

US07228064B2 Image decoding apparatus, recording medium which computer can read from, and program which computer can read 失效
标题翻译：图像解码装置，计算机可读取的记录介质，以及计算机可读取的程序
公开(公告)号：US07228064B2
公开(公告)日：2007-06-05
申请号：US10211716
申请日：2002-08-02
申请人： Yoshiyuki Wada , Makoto Hirai , Tokuzo Kiyohara , Kosuke Yoshioka , Hideshi Nishida , Yukiharu Ieda
发明人： Yoshiyuki Wada , Makoto Hirai , Tokuzo Kiyohara , Kosuke Yoshioka , Hideshi Nishida , Yukiharu Ieda
IPC分类号： H04N7/26 , H03N7/40
CPC分类号： H04N9/7921 , H04N5/78266 , H04N9/8042 , H04N9/8047 , H04N19/42
摘要： The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.
摘要翻译：本发明提供一种图像解码装置，其实现从由第一DCT块和MR组成的固定长度单元取出MR（宏块余数）的加速处理，而不增加成本。安装处理器3输出构成SB（同步块）的多个固定长度单元中的一个。首先，从固定长度单位的开始到包括在固定长度单位中的EOB（块末尾）的长度进行计算。然后将计算出的长度用作取出MR的偏移量。然后，包括在MR中的第二DCT块的结束部分与第二DCT块的对应开始部分组合，以便获得完整的第二DCT块。完整的第二DCT块被输出到可变长度码解码器13。

4. 发明授权

US06829302B2 Pixel calculating device 有权
标题翻译：像素计算装置
公开(公告)号：US06829302B2
公开(公告)日：2004-12-07
申请号：US10019498
申请日：2001-12-20
申请人： Hiroyuki Morishita , Kosuke Yoshioka , Hideshi Nishida , Makoto Hirai , Ryuji Matsuura , Toshiaki Tsuji , Kozo Kimura , Tokuzo Kiyohara
发明人： Hiroyuki Morishita , Kosuke Yoshioka , Hideshi Nishida , Makoto Hirai , Ryuji Matsuura , Toshiaki Tsuji , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： H04N712
CPC分类号： H04N19/80 , G06T3/4007 , G06T3/4023 , G06T5/20 , G06T2200/28
摘要： A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.
摘要翻译：一种对像素数据进行垂直滤波以便在垂直方向上减少帧数据的像素计算装置。像素计算装置包括用于解码压缩视频数据以产生帧数据的解码单元401，用于存储帧数据的帧存储器402，用于通过垂直滤波减少垂直方向上的帧数据以产生缩小图像的滤波单元403 用于存储从滤波单元403输出的缩小图像的缓冲存储器404，以及基于解码单元401的视频数据的解码状态和滤波单元403的帧数据的滤波状态来控制滤波单元403的控制单元406 ，因此在过滤单元403中不会发生溢出和欠载。

5. 发明授权

US06809777B2 Pixel calculating device 有权
标题翻译：像素计算装置
公开(公告)号：US06809777B2
公开(公告)日：2004-10-26
申请号：US10019419
申请日：2001-12-18
申请人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara , Makoto Hirai , Kozo Kimura , Ryuji Matsuura , Hiroyuki Morishita , Toshiaki Tsuji
发明人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara , Makoto Hirai , Kozo Kimura , Ryuji Matsuura , Hiroyuki Morishita , Toshiaki Tsuji
IPC分类号： H04N964
CPC分类号： H04N19/80 , G06T1/20 , G06T5/20
摘要： A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.
摘要翻译：用于执行垂直滤波的像素计算装置，其包括16个像素处理单元1至16以及存储16个像素数据和滤波器系数的输入缓冲器组22。每个像素处理单元使用从输入缓冲器组22提供的像素数据和滤波器系数来执行操作，然后从邻近的像素处理单元获取像素数据。使用所获取的像素数据由每个像素处理单元执行进一步的操作，并且累积运算结果。通过重复该获取和累积过程来进行过滤，抽头的数量由重复次数确定。

6. 发明申请

US20050238095A1 Transcoder 失效
标题翻译：转码器
公开(公告)号：US20050238095A1
公开(公告)日：2005-10-27
申请号：US10686237
申请日：2003-10-15
申请人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
发明人： Kosuke Yoshioka , Makoto Hirai , Tetsuji Mochida , Hiroyuki Oka , Hideshi Nishida , Tokuzo Kiyohara
IPC分类号： G06T3/40 , H04N7/12 , H04N7/26 , H04N7/46 , H04N7/50
CPC分类号： G06T3/40 , H04N19/16 , H04N19/40 , H04N19/42 , H04N19/59 , H04N19/61
摘要： A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.
摘要翻译：一种用于调整视频数据大小并将调整大小的视频数据输出到再现设备的代码转换器。再现装置通过重复显示周期和非显示周期交替地再现调整大小的视频数据。代码转换器包括：调整大小的视频数据的调整大小; 以及控制单元，其使所述调整大小单元将所述视频数据的大小调整为具有第一分辨率的第一视频数据，使得所述再现设备在每个显示周期期间显示一个图像，并且使得调整大小单元在调整大小将视频数据提供给第一视频数据，将视频数据转换为具有低于第一分辨率的第二分辨率的第二视频数据。

7. 发明授权

US06414608B1 Variable length code decoding device, digital broadcast receiving apparatus, and DVD reproducing apparatus 有权
标题翻译：可变长码解码装置，数字广播接收装置和DVD再现装置
公开(公告)号：US06414608B1
公开(公告)日：2002-07-02
申请号：US09583374
申请日：2000-05-31
申请人： Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
发明人： Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
IPC分类号： H03M740
CPC分类号： H04N19/436 , H04N19/61 , H04N19/91
摘要： A first bit string extracting unit extracts a first bit string. A first bit length judging unit detects a first codeword from the first bit string. A first decoding unit generates a first run-level pair from the first codeword. A second bit string extracting unit extracts a second bit string. A second bit length judging unit detects a second codeword from the second bit string. A second decoding unit generates a second run-level pair from the second codeword. A first inverse quantizing unit inverse quantizes the first level to obtain a DCT coefficient. A second inverse quantizing unit inverse quantizes the second level to obtain a DCT coefficient. A second buffer controller writes the DCT coefficients and their first buffer addresses into a second buffer. A first buffer controller reads the DCT coefficients and the first buffer addresses from the second buffer and writes the DCT coefficients into a first buffer at the respective first buffer addresses.
摘要翻译：第一位串提取单元提取第一位串。第一比特长度判断单元从第一比特串检测第一码字。第一解码单元从第一码字生成第一游程级对。第二位串提取单元提取第二位串。第二位长度判断单元从第二位串检测第二码字。第二解码单元从第二码字生成第二游程级对。第一反量化单元逆量化第一电平以获得DCT系数。第二反量化单元逆量化第二电平以获得DCT系数。第二缓冲器控制器将DCT系数及其第一缓冲器地址写入第二缓冲器。第一缓冲器控制器从第二缓冲器读取DCT系数和第一缓冲器地址，并将DCT系数写入相应的第一缓冲器地址的第一缓冲器。

8. 发明申请

US20050018914A1 Pixel processing circuit, decoding apparatus, and pixel processing method 审中-公开
标题翻译：像素处理电路，解码装置和像素处理方法
公开(公告)号：US20050018914A1
公开(公告)日：2005-01-27
申请号：US10865416
申请日：2004-06-10
申请人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
发明人： Hiroyuki Oka , Hideshi Nishida , Kosuke Yoshioka , Tokuzo Kiyohara
IPC分类号： H04N19/50 , G06K9/36 , G06T1/20 , H04N19/105 , H04N19/20 , H04N19/21 , H04N19/423 , H04N19/59
CPC分类号： G06T1/20 , G06T9/20 , H04N19/20 , H04N19/42 , H04N19/44 , H04N19/61
摘要： The invention provides a circuit used in a padding and other processes necessary for coding of objects, and performs at high speed pixel processing to generate pixel values to be assigned to cells, using pixel values in a reference area, which includes cells with and without a pixel value. A cell address outputting unit (i) obtains cell addresses indicating positions of a predetermined number of cells serially arranged and binary signals expressing whether those cells each have a pixel value, and (ii) selects, for each cell, two of the obtained cell addresses corresponding to a part of binary signals each expressing that a cell has a pixel value, and outputs the selected cell addresses. A reading unit reads pixel values of the cells at the outputted cell addresses. An operating unit calculates the average of the two read pixel values and outputs the average as a pixel value.
摘要翻译：本发明提供了一种用于填充和其他对象编码所需的处理的电路，并使用参考区域中的像素值在高速像素处理中执行以分配给单元的像素值，该电路包括具有和不具有像素值。单元地址输出单元（i）获得指示串行排列的预定数量的单元的位置的单元地址，以及表示这些单元是否具有像素值的二进制信号，以及（ii）为每个单元选择两个获得的单元地址对应于每个表示单元具有像素值的二进制信号的一部分，并输出所选择的单元地址。读取单元读取输出的单元地址处的单元的像素值。操作单元计算两个读取像素值的平均值，并将该平均值作为像素值输出。

9. 发明授权

US06470376B1 Processor capable of efficiently executing many asynchronous event tasks 失效
标题翻译：处理器能够有效地执行许多异步事件任务
公开(公告)号：US06470376B1
公开(公告)日：2002-10-22
申请号：US09034198
申请日：1998-03-03
申请人： Takaharu Tanaka , Kiyoshi Maenobu , Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara
发明人： Takaharu Tanaka , Kiyoshi Maenobu , Kosuke Yoshioka , Makoto Hirai , Tokuzo Kiyohara
IPC分类号： G06F900
CPC分类号： G06F9/4881 , G06F9/30087 , G06F9/3009 , G06F9/3851 , H04N19/42 , H04N19/61
摘要： The counter 52 is set with an initial value of “1” and is a counter with a maximum value of “4”. This counter 52 increments the count value held by the flip-flop 51 in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1,2,3,4. This clock signal is also used by the instruction decode control unit 11 to control the execution of instructions, with the counting by the counter 52 being performed once for each instruction execution performed by the instruction decode control unit 11. The comparator 54 compares the count value counted by the counter 52 with the maximum value “4”, and when the values match, sets the task switching signal chg_task_ex at a “High” value, so that the processing switches to the execution of the next task.
摘要翻译：计数器52被设置为初始值“1”，并且是具有最大值“4”的计数器。该计数器52与时钟信号同步地增加由触发器51保持的计数值，使得计数值如进展1,2,3,4,1,2,3,4所示变化。指令解码控制单元11还使用该时钟信号来控制指令的执行，计数器52对由指令解码控制单元11进行的每个指令执行一次执行一次计数。比较器54将计数值由具有最大值“4”的计数器52计数，并且当该值匹配时，将任务切换信号chg_task_ex设置为“高”值，使得处理切换到下一任务的执行。

10. 发明授权

US07594099B2 Processor executing SIMD instructions 有权
标题翻译：处理器执行SIMD指令
公开(公告)号：US07594099B2
公开(公告)日：2009-09-22
申请号：US11896368
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/305
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC0〜VC3（110）全部为零，并且（i）设置条件标志C4 当所有向量条件标志VC0〜VC3都为零时，分别将条件标志寄存器（CFR）32至1和0分别设置为条件标志寄存器（CFR）32和C5，以及（ii）分别将条件标志C4和C5设置为0和1，并非所有向量条件标志都为零。然后，矢量条件标志VC0〜VC3被存储在条件标志C0〜C3中。

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