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1. 发明授权

US5184204A Semiconductor device with high surge endurance 失效
标题翻译：具有高浪涌耐久性的半导体器件
公开(公告)号：US5184204A
公开(公告)日：1993-02-02
申请号：US645872
申请日：1991-01-24
申请人： Teruyoshi Mihara , Tsutomu Matsushita , Kenji Yao , Masakatsu Hoshi , Yutaka Enokido , Yukitsugu Hirota
发明人： Teruyoshi Mihara , Tsutomu Matsushita , Kenji Yao , Masakatsu Hoshi , Yutaka Enokido , Yukitsugu Hirota
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7808 , H01L29/0619 , H01L29/0626 , H01L29/0696 , H01L29/1095 , H01L29/0878
摘要： A semiconductor device in which the breakdown voltages of the cell unit and the guard ring can easily be matched, and the surge endurance of the device can be improved. This semiconductor device includes a guard ring region surrounding the cell diffusion layers which is formed from an array of a plurality of guard ring cells, where each of the guard ring cells is identical to each of the cell diffusion layers and the guard ring cells are electrically connected mutually, so that the diffusion depths of each of the cells of the guard ring region and the cell diffusion layers are identical, and consequently the breakdown voltages for the guard ring region and the cell diffusion layers can be made equal to each other.
摘要翻译：可以容易地匹配电池单元和保护环的击穿电压的半导体器件，并且可以提高器件的浪涌耐久性。该半导体器件包括围绕由多个保护环电池的阵列形成的电池扩散层的保护环区域，其中每个保护环电池与每个电池扩散层相同，保护环电池为电相互连接，使得保护环区域和电池扩散层的每个电池的扩散深度相同，因此保护环区域和电池扩散层的击穿电压可以彼此相等。

2. 发明授权

US5192989A Lateral DMOS FET device with reduced on resistance 失效
标题翻译：具有降低耐电压性能的侧面DMOS FET器件
公开(公告)号：US5192989A
公开(公告)日：1993-03-09
申请号：US618358
申请日：1990-11-27
申请人： Tsutomu Matsushita , Teruyoshi Mihara , Masakatsu Hoshi , Kenji Yao
发明人： Tsutomu Matsushita , Teruyoshi Mihara , Masakatsu Hoshi , Kenji Yao
IPC分类号： H01L29/06 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/7801 , H01L29/0696 , H01L29/41758
摘要： A lateral DMOS FET device which has a small on resistance. The device includes a cell structure formed by a plurality of unit cells, each unit cell including: a source region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the source region; and a plurality of drain contact regions of first conduction type located around the channel region; and a source electrode, a gate electrode, and a drain electrode, all of which are formed on the same one side of the substrate. Alternatively, each unit cell may includes: a drain contact region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the drain contact region; and a plurality of source regions of first conduction type located around the channel region.
摘要翻译：具有导通电阻小的横向DMOS FET器件。该装置包括由多个单元电池形成的单元结构，每个单位单元包括：形成在第一导电类型的基板的一侧的第一导电类型的源区; 形成在源极区周围的第二导电类型的沟道区; 以及位于所述沟道区周围的多个第一导电类型的漏极接触区域; 以及源电极，栅极电极和漏电极，所有这些都形成在基板的相同的一侧上。或者，每个单电池可以包括：形成在第一导电类型的衬底的一侧上的第一导电类型的漏极接触区域; 形成在所述漏极接触区域周围的第二导电类型的沟道区域; 以及位于沟道区周围的多个第一导电类型的源极区。

3. 发明授权

US5049953A Schottky tunnel transistor device 失效
标题翻译：肖特基隧道晶体管器件
公开(公告)号：US5049953A
公开(公告)日：1991-09-17
申请号：US465750
申请日：1990-01-18
申请人： Teruyoshi Mihara , Kenji Yao , Tsutomu Matsushita , Yoshinori Murakami
发明人： Teruyoshi Mihara , Kenji Yao , Tsutomu Matsushita , Yoshinori Murakami
IPC分类号： H01L29/739 , H01L29/78 , H01L29/48 , H01L27/02 , H01L29/10 , H01L29/34
CPC分类号： H01L29/7839 , Y10S257/902
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, in which a drain region is formed in the substrate, and a gate electrode is formed on the surface of the substrate via an insulating film formed thereon. A Schottky metal as a source region is formed in the surface of the substrate away from the drain region, the Schottky metal and the substrate constituting a Schottky junction at an interface therebetween near the gate electrode. A shield layer of a second conductivity type is interposed between the Schottky metal and the substrate except in the Schottky junction. The gate electrode controls tunnel current at the Schottky junction.
摘要翻译：半导体器件包括：第一导电类型的半导体衬底，其中在衬底中形成漏极区，并且通过形成在其上的绝缘膜在衬底的表面上形成栅电极。作为源极区域的肖特金属金属在远离漏极区域的肖特基金属和衬底的与栅极电极附近的界面处构成肖特基结的表面上形成。第二导电类型的屏蔽层介于除了肖特基结之外的肖特基金属和基板之间。栅电极控制肖特基结的隧道电流。

4. 发明授权

US4937639A Input protector device for semiconductor device 失效
标题翻译：半导体器件输入保护器
公开(公告)号：US4937639A
公开(公告)日：1990-06-26
申请号：US257577
申请日：1988-10-14
申请人： Kenji Yao , Teruyoshi Mihara , Noriyuki Abe , Tsutomu Matsushita
发明人： Kenji Yao , Teruyoshi Mihara , Noriyuki Abe , Tsutomu Matsushita
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/08 , H01L27/092 , H01L27/118
CPC分类号： H01L27/0251 , H01L27/0921 , H01L27/11898
摘要： An input protector device for a semiconductor device such as a CMOS device, in which a first resistor is formed on an insulating film of a semiconductor substrate, and a second resistor is formed of an impurity diffusion region in the substrate, the first and second resistors and a capacitor being coupled to one another in series to constitute a filter circuit, and in which first and second diodes each cooperated with at least one of the first and second resistors, by-passing noises having low and high voltages, respectively, and a high frequency noise is cut by the filter circuit, thereby effectively preventing latchup.

5. 发明授权

US5040034A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5040034A
公开(公告)日：1991-08-13
申请号：US465748
申请日：1990-01-18
申请人： Yoshinori Murakami , Teruyoshi Mihara , Tsutomu Matsushita , Kenji Yao , Norihiko Kiritani
发明人： Yoshinori Murakami , Teruyoshi Mihara , Tsutomu Matsushita , Kenji Yao , Norihiko Kiritani
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L29/7839 , Y10S257/902
摘要： A semiconductor device includes a semiconductor substrate as a drain region. A metal source region is located on a first surface of the substrate. The metal and the substrate constitute a Schottky junction. An insulated gate, including a gate electrode and an insulating film surrounding the gate electrode, is adjacent to the Schottky junction, such that angle formed by the Schottky junction and the insulated gate in the substrate is an acute angle. A part of the Schottky metal can be buried in the form of a pillar in the substrate, and a channel region of the Schottky junction can be formed on the pillar near the insulated gate.
摘要翻译：半导体器件包括作为漏极区域的半导体衬底。金属源区位于基板的第一表面上。金属和衬底构成肖特基结。包括栅电极和围绕栅电极的绝缘膜的绝缘栅极与肖特基结相邻，使得由肖特基结和衬底中的绝缘栅极形成的角度是锐角。肖特基金属的一部分可以以衬底的形式被埋入，并且可以在绝缘栅极附近的柱上形成肖特基结的沟道区。

6. 发明授权

US4920396A CMOS having buried layer for carrier recombination 失效
标题翻译： CMOS具有用于载流子复合的掩埋层
公开(公告)号：US4920396A
公开(公告)日：1990-04-24
申请号：US179315
申请日：1988-04-08
申请人： Toshiro Shinohara , Teruyoshi Mihara , Kenji Yao
发明人： Toshiro Shinohara , Teruyoshi Mihara , Kenji Yao
IPC分类号： H01L27/08 , H01L21/18 , H01L27/092
CPC分类号： H01L21/187 , H01L27/0921
摘要： In order to improve latchup withstanding capability, a CMOS device is provided with at least one recombination layer which is buried in either or both substrate regions of a pMOS and a nMOS at such a position that a depletion layer formed at a pn junction between both substrate regions of the pMOS and nMOS does not reach the recombination layer. The recombination layer is a polycrystalline silicon or amorphous silicon layer having plentiful carrier recombination centers, or a layer having plentiful traps formed by ion implantation, or a layer of a compound semiconductor having a small band gap.
摘要翻译：为了提高闭锁保护能力，CMOS器件提供有至少一个复合层，其被埋在pMOS和nMOS的一个或两个衬底区域中，在这样的位置处，在两个衬底之间的pn结处形成的耗尽层 pMOS和nMOS的区域不会到达复合层。复合层是具有多个载流子复合中心的多晶硅或非晶硅层，或具有通过离子注入形成的大量陷阱的层或具有小带隙的化合物半导体层。

7. 发明授权

US4805008A Semiconductor device having MOSFET and deep polycrystalline silicon region 失效
标题翻译：具有MOSFET和深多晶硅区域的半导体器件
公开(公告)号：US4805008A
公开(公告)日：1989-02-14
申请号：US64852
申请日：1987-06-22
申请人： Kenji Yao , Teruyoshi Mihara
发明人： Kenji Yao , Teruyoshi Mihara
IPC分类号： H01L27/08 , H01L27/092 , H01L29/78 , H01L27/02 , H01L29/04
CPC分类号： H01L27/0921
摘要： A semiconductor device such as a CMOS is provided with highly doped polycrystalline silicon regions for preventing undesired operations of parasitic transistors. Each polycrystalline region is extended deeper from a top surface of the silicon chip than source and drain regions of MOS transistors. In a substrate region of each MOS, one polycrystalline region of the same conductivity type as the substrate region is formed near the source region, and connected with said source region so that the polycrystalline region is held equipotential with the source region.
摘要翻译：诸如CMOS的半导体器件被提供有高掺杂多晶硅区域，用于防止寄生晶体管的不期望的操作。每个多晶区域从硅芯片的顶表面比MOS晶体管的源极和漏极区域更深地延伸。在每个MOS的衬底区域中，在源极区附近形成与衬底区域相同的导电类型的一个多晶区域，并且与所述源极区域连接，使得多晶区域保持与源极区域等电位。

8. 发明授权

US08476347B1 Resin compound, resin composition, and resin-molded article 有权
标题翻译：树脂组合物，树脂组合物和树脂模制品
公开(公告)号：US08476347B1
公开(公告)日：2013-07-02
申请号：US13485087
申请日：2012-05-31
申请人： Kenji Yao
发明人： Kenji Yao
IPC分类号： C08K5/523
CPC分类号： C08G69/48 , C08G63/912 , C08G63/914 , C08L77/02 , C08L77/06 , G03G5/056 , G03G5/0571 , G03G5/0589 , C08L61/06
摘要： A resin compound includes a reaction product of (A) polymer which is at least selected from aliphatic polyester and aliphatic polyamide and (B) an aromatic compound with a compositional ratio from 0.1 to 10 parts by weight with respect to 100 parts by weight of (A) and represented by the following Formula (1): wherein each of R1, R2, and R3 represents a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 6 carbon atoms, or a substituted or unsubstituted aromatic group having 6 to 10 carbon atoms; each of R4, R5, R6, and R7 represents a substituted or unsubstituted alkyl group having 1 to 6 carbon atoms or a substituted or unsubstituted aromatic group having 6 to 10 carbon atoms; each dm and n independently represents an integer from 0 to 3; and each of p and q represents an integer from 0 to 4.
摘要翻译：树脂化合物包括（A）至少选自脂族聚酯和脂族聚酰胺的聚合物的反应产物和（B）组成比为0.1-10重量份的芳族化合物相对于100重量份的 A）表示，并且由下式（1）表示：其中R 1，R 2和R 3各自表示氢原子，取代或未取代的碳原子数1〜6的烷基或取代或未取代的6〜10的芳基碳原子 R4，R5，R6和R7各自表示取代或未取代的碳原子数为1〜6的烷基或取代或未取代的碳原子数为6〜10的芳香族基团。每个dm和n独立地表示0至3的整数; p和q各自表示0〜4的整数。

9. 发明授权

US08455575B2 Wood powder-containing material, method of manufacturing the same, and compact 有权
标题翻译：含木粉的材料，其制造方法和紧凑
公开(公告)号：US08455575B2
公开(公告)日：2013-06-04
申请号：US13358604
申请日：2012-01-26
申请人： Kenji Yao
发明人： Kenji Yao
IPC分类号： C08L97/02
CPC分类号： C08L97/02 , C08K5/523 , C08L67/02 , C08L67/04
摘要： A wood powder-containing material includes wood powder having a volume average particle diameter of from about 1 μm to about 5 mm, an aliphatic polyester, and a condensed phosphate ester.
摘要翻译：含有木粉的材料包括体积平均粒径为约1μm至约5mm的木粉，脂族聚酯和缩合磷酸酯。

10. 发明授权

US08445602B2 Poly lactic acid resin, resin composition, and resin molding 有权
标题翻译：聚乳酸树脂，树脂组合物和树脂成型
公开(公告)号：US08445602B2
公开(公告)日：2013-05-21
申请号：US12941480
申请日：2010-11-08
申请人： Kenji Yao
发明人： Kenji Yao
IPC分类号： C08G63/91
CPC分类号： C08G63/64 , C08G63/08 , C08L23/10 , C08L67/04 , C08L69/00 , C08L77/00 , C08L2666/06 , C08L2666/18 , C08L2666/20
摘要： The present invention provides a poly lactic acid resin including an L-lactic acid block and a D-lactic acid block, which blocks are bonded by a carbonate bonding.
摘要翻译：本发明提供了包含L-乳酸嵌段和D-乳酸嵌段的聚乳酸树脂，该嵌段通过碳酸酯键合而键合。

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