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    • 6. 发明授权
    • Counting circuit with rewritable non-volatile memory, and counting method
    • 具有可重写非易失性存储器的计数电路和计数方法
    • US06314155B1
    • 2001-11-06
    • US09166846
    • 1998-10-06
    • Yoshihiro ShonaSeiichi YamazakiKeiichi Itoh
    • Yoshihiro ShonaSeiichi YamazakiKeiichi Itoh
    • G06M300
    • H03K21/403
    • A frequency counter 1 includes a binary counter section 11 having a binary counter 20 for counting up frequency data, and a EEPROM counter section 12 having an EEPROM 40 containing frequency data. In a frequency count processing, frequency data of the EEPROM 40 are loaded into the binary counter 20. The binary counter 20 executes count up by a specified frequency on the loaded frequency data. The counted up frequency data are written into the EEPROM 40 to update the frequency data of the EEPROM 40. In one frequency count process, rewriting of the EEPROM 40 is completed once, which means that the number of time the EEPROM 40 is rewritten is reduced.
    • 频率计数器1包括具有用于计数上位频率数据的二进制计数器20的二进制计数器部分11和具有包含频率数据的EEPROM 40的EEPROM计数器部分12。 在频率计数处理中,EEPROM 40的频率数据被加载到二进制计数器20中。二进制计数器20对加载的频率数据执行向上计数指定的频率。 计数上升频率数据被写入EEPROM 40以更新EEPROM 40的频率数据。在一个频率计数过程中,EEPROM 40的重写完成一次,这意味着EEPROM 40被重写的时间减少 。
    • 7. 发明授权
    • Method of forming improved matted surface-finished article by use of
transfer member, and article formed thereby
    • 通过使用转印构件形成改良的无光泽表面处理制品的方法和由此形成的制品
    • US5639536A
    • 1997-06-17
    • US308958
    • 1994-09-20
    • Seiichi YamazakiNaoto Toyooka
    • Seiichi YamazakiNaoto Toyooka
    • B29C45/14B32B3/30
    • B29C45/14811B29C45/1418B29C45/14827Y10S428/914Y10T428/24355Y10T428/24479Y10T428/24521Y10T428/24612Y10T428/28Y10T428/2817Y10T428/2839
    • An in-mold molded product includes a molded plastic member having projections and recesses on a surface thereof and a transfer layer provided on such surface. The outer surface of the transfer layer has a contour corresponding to the projections and recesses of the plastic member and additionally has projections and recesses that are finer than those on the surface of the plastic molded member. Thus, the finished product has a matte surface with good wear characteristics. The product is molded by arranging a mat transfer member at a predetermined region of a cavity of a mold unit, the mat transfer member having the fine projections and recesses on one surface thereof, and a portion of the mold unit defining the cavity having, at the predetermined region, projections and recesses which are larger in size than those of the mat transfer member. Plastic is injected into the cavity in a direction to urge the mat transfer member against the portion of the mold unit having the larger projections and recesses thus molding the molded product.
    • 模内成型产品包括在其表面上具有突出和凹陷的模制塑料构件和设置在该表面上的转移层。 转印层的外表面具有与塑料构件的突起和凹部对应的轮廓,并且还具有比塑料模制构件的表面上更细的凹凸。 因此,成品具有具有良好磨损特性的无光泽表面。 该产品通过在模具单元的空腔的预定区域处布置垫子转移构件来模制,所述垫子转移构件在其一个表面上具有微细的突起和凹部,并且限定空腔的模具单元的一部分在 所述预定区域,尺寸大于所述垫转印构件的尺寸。 将塑料沿着一个方向注入空腔中,以促使垫转移构件抵靠具有较大突出和凹陷的模具单元的部分,从而模制成型产品。
    • 8. 发明授权
    • Analog switch with minimized noise ascribable to gate capacitance
    • 具有归因于栅极电容的最小化噪声的模拟开关
    • US4962413A
    • 1990-10-09
    • US230234
    • 1988-08-09
    • Seiichi YamazakiHiroaki InoueSumihiro TakashimaHiroshisa Shishikura
    • Seiichi YamazakiHiroaki InoueSumihiro TakashimaHiroshisa Shishikura
    • H01L29/78G02F1/136G02F1/1368G11C27/02H01L21/8234H01L27/088H01L27/092H03K17/14H03K17/16H03K17/687
    • H03K17/145H01L27/092H03K17/162
    • An analog switch includes n-channel and p-channel MOSFETs formed in a surface of a semiconductor substrate. Each of the n-channel and p-channel MOSFETs has first, second and third diffused regions which are formed in the semiconductor surface with the width thereof substantially equal to each other. The first and third diffused regions are spaced from the second diffused region to form first and second channel regions, respectively. Each of the n-channel and p-channel MOSFETs has first and second gate electrodes which are interconnected in common to each other and placed on respective gate insulating layers overlaying the first and second channel regions, respectively. The first gate electrode has an end portion extending over part of the second diffused region by a predetermined length, while the second gate electrode has an end portion extending over another part, opposite to the earlier-mentioned part, of the second diffused region by a predetermined length. A sample and hold circuit including the analog switch is also provided.
    • 模拟开关包括形成在半导体衬底的表面中的n沟道和p沟道MOSFET。 n沟道和p沟道MOSFET中的每一个具有第一,第二和第三扩散区,其形成在半导体表面中,其宽度基本上彼此相等。 第一和第三扩散区域与第二扩散区域分开形成第一和第二通道区域。 n沟道和p沟道MOSFET中的每一个具有第一和第二栅电极,这些第一和第二栅极电极彼此共同互连并分别放置在覆盖第一和第二沟道区的相应的栅极绝缘层上。 第一栅极电极具有在第二扩散区域的一部分上延伸预定长度的端部,而第二栅电极具有在第二扩散区域的与较早提及的部分相对的另一部分上延伸的端部, 预定长度。 还提供了包括模拟开关的采样和保持电路。