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1. 发明授权

US06324341B1 Lot-to-lot rapid thermal processing (RTP) chamber preheat optimization 有权
标题翻译：批量快速热处理（RTP）室预热优化
公开(公告)号：US06324341B1
公开(公告)日：2001-11-27
申请号：US09559147
申请日：2000-04-26
申请人： Terrence J. Riley , Qingsu Wang , Michael Miller , William Jarrett Campbell , Jeff Thompson
发明人： Terrence J. Riley , Qingsu Wang , Michael Miller , William Jarrett Campbell , Jeff Thompson
IPC分类号： F26B1900
CPC分类号： H01L21/67115 , H01L21/67248
摘要： A method is provided, the method comprising preheating a rapid thermal processing chamber according to a preheating recipe and processing a first plurality of workpieces in the rapid thermal processing chamber. The method also comprises performing first parameter measurements on first and second workpieces of the first plurality of workpieces, the first parameter measurements indicative of first processing differences between the first and second workpieces, and forming a first output signal corresponding to the first parameter measurements. The method further comprises adjusting the preheating recipe based on the first output signal and using the adjusted preheating recipe to preheat the rapid thermal processing chamber for processing a second plurality of workpieces in the rapid thermal processing chamber to reduce second processing differences between first and second workpieces of the second plurality of workpieces.
摘要翻译：提供了一种方法，该方法包括根据预热配方预热快速热处理室并处理快速热处理室中的第一多个工件。该方法还包括对第一多个工件的第一和第二工件执行第一参数测量，第一参数测量指示第一和第二工件之间的第一处理差异，以及形成对应于第一参数测量的第一输出信号。该方法还包括基于第一输出信号调整预热配方并使用经调节的预热配方来预热快速热处理室以处理快速热处理室中的第二多个工件，以减少第一和第二工件之间的第二处理差异的第二多个工件。

2. 发明授权

US06268270B1 Lot-to-lot rapid thermal processing (RTP) chamber preheat optimization 有权
标题翻译：批量快速热处理（RTP）室预热优化
公开(公告)号：US06268270B1
公开(公告)日：2001-07-31
申请号：US09429790
申请日：1999-10-29
申请人： Glen W. Scheid , Terrence J. Riley , Qingsu Wang , Michael Miller , Si-Zhao J. Qin
发明人： Glen W. Scheid , Terrence J. Riley , Qingsu Wang , Michael Miller , Si-Zhao J. Qin
IPC分类号： H01C21265
CPC分类号： G01J5/0003 , G01J1/32
摘要： Methods of optimizing a preheat recipe for rapid thermal processing workpieces are provided. In one aspect, a method of manufacturing is provided that includes preheating a rapid thermal processing chamber according to a preheating recipe and processing a first plurality of workpieces in the rapid thermal processing chamber. Parameter measurements are performed on a first workpiece and a second workpiece of the first plurality of workpieces. The parameter measurements are indicative of processing differences between the first and second workpieces. An output signal is formed corresponding to the parameter measurements and a control signal based on the output signal is used to adjust the preheating recipe for preheating the rapid thermal processing chamber for processing a second plurality of workpieces in the rapid thermal processing chamber to reduce processing differences between first and second workpieces of the second plurality of workpieces.
摘要翻译：提供了优化用于快速热处理工件的预热配方的方法。一方面，提供一种制造方法，其包括根据预热配方预热快速热处理室并在快速热处理室中处理第一多个工件。在第一工件和第一工件的第二工件上执行参数测量。参数测量表示第一和第二工件之间的加工差异。对应于参数测量形成输出信号，并且使用基于输出信号的控制信号来调节用于预热快速热处理室的预热配方，用于处理快速热处理室中的第二多个工件以减少加工差异在第二多个工件的第一和第二工件之间。

3. 发明授权

US06856849B2 Method for adjusting rapid thermal processing (RTP) recipe setpoints based on wafer electrical test (WET) parameters 失效
标题翻译：基于晶圆电测试（WET）参数调整快速热处理（RTP）配方设定点的方法
公开(公告)号：US06856849B2
公开(公告)日：2005-02-15
申请号：US09731579
申请日：2000-12-06
申请人： Terrence J. Riley , William Jarrett Campbell
发明人： Terrence J. Riley , William Jarrett Campbell
IPC分类号： H01L21/66 , G08F19/00
CPC分类号： H01L22/20
摘要： A method is provided, the method comprising measuring at least one parameter characteristic of processing performed on a workpiece in a processing step, and modeling the at least one characteristic parameter measured using a correlation model. The method also comprises applying the correlation model to modify the processing performed in the processing step.
摘要翻译：提供了一种方法，所述方法包括在处理步骤中测量在工件上执行的处理的至少一个参数特征，以及对使用相关模型测量的所述至少一个特征参数进行建模。该方法还包括应用相关模型来修改在处理步骤中执行的处理。

4. 发明授权

US06819963B2 Run-to-run control method for proportional-integral-derivative (PID) controller tuning for rapid thermal processing (RTP) 有权
标题翻译：用于快速热处理（RTP）的比例积分微分（PID）控制器调谐的运行控制方法
公开(公告)号：US06819963B2
公开(公告)日：2004-11-16
申请号：US09732187
申请日：2000-12-06
申请人： Terrence J. Riley , William Jarrett Campbell
发明人： Terrence J. Riley , William Jarrett Campbell
IPC分类号： G06F1900
CPC分类号： G05B13/042 , G05B11/42
摘要： A method is provided, the method comprising measuring at least one parameter characteristic of rapid thermal processing performed on a workpiece in a rapid thermal processing step, and modeling the at least one characteristic parameter measured using a first-principles radiation model. The method also comprises applying the first-principles radiation model to modify the rapid thermal processing performed in the rapid thermal processing step.
摘要翻译：提供了一种方法，该方法包括测量在快速热处理步骤中对工件进行的快速热处理的至少一个参数特征，以及对使用第一原理辐射模型测量的至少一个特征参数进行建模。该方法还包括应用第一原理辐射模型来修改在快速热处理步骤中执行的快速热处理。

5. 发明授权

US06697691B1 Method and apparatus for fault model analysis in manufacturing tools 失效
标题翻译：制造工具中故障模型分析的方法和装置
公开(公告)号：US06697691B1
公开(公告)日：2004-02-24
申请号：US09476895
申请日：2000-01-03
申请人： Michael L. Miller , Terrence J. Riley , Qingsu Wang
发明人： Michael L. Miller , Terrence J. Riley , Qingsu Wang
IPC分类号： G06F1900
CPC分类号： H01L22/20
摘要： The present invention provides for a method and an apparatus for fault model analysis in manufacturing tools. A sequence of semiconductor devices is processed through a manufacturing process. Production data resulting from the processing of the semiconductor devices is acquired. A fault model analysis is performed using the acquired production data.
摘要翻译：本发明提供了制造工具中的故障模型分析的方法和装置。通过制造工艺处理一系列半导体器件。获取由半导体器件的处理产生的生产数据。使用获取的生产数据进行故障模型分析。

6. 发明授权

US06725402B1 Method and apparatus for fault detection of a processing tool and control thereof using an advanced process control (APC) framework 有权
标题翻译：用于处理工具的故障检测的方法和装置及其使用先进的过程控制（APC）框架进行控制
公开(公告)号：US06725402B1
公开(公告)日：2004-04-20
申请号：US09629073
申请日：2000-07-31
申请人： Elfido Coss, Jr. , Qingsu Wang , Terrence J. Riley
发明人： Elfido Coss, Jr. , Qingsu Wang , Terrence J. Riley
IPC分类号： G06F1100
CPC分类号： G05B19/4184 , G05B19/41875 , G05B2219/32209 , G05B2219/32221 , Y02P90/02 , Y02P90/14 , Y02P90/22
摘要： A method and apparatus for providing fault detection in an Advanced Process Control (APC) framework. A first interface receives operational state data of a processing tool related to the manufacture of a processing piece. The state data is sent from the first interface to a fault detection unit. A fault detection unit determines if a fault condition exists with the processing tool based upon the state data. A predetermined action is performed on the processing tool in response to the presence of a fault condition. In accordance with one embodiment, the predetermined action is to shutdown the processing tool so as to prevent further production of faulty wafers.
摘要翻译：一种用于在高级过程控制（APC）框架中提供故障检测的方法和装置。第一接口接收与制造加工件相关的加工工具的操作状态数据。状态数据从第一接口发送到故障检测单元。故障检测单元基于状态数据确定处理工具是否存在故障状况。响应于故障状况的存在，对处理工具执行预定的动作。根据一个实施例，预定的动作是关闭处理工具，以防止进一步生产故障晶片。

7. 发明授权

US06738731B1 Method and apparatus for using tool state information to identify faulty wafers 有权
标题翻译：使用工具状态信息来识别故障晶片的方法和装置
公开(公告)号：US06738731B1
公开(公告)日：2004-05-18
申请号：US09815445
申请日：2001-03-22
申请人： Terrence J. Riley , Qingsu Wang , Glen W. Scheid , Kent F. Knox
发明人： Terrence J. Riley , Qingsu Wang , Glen W. Scheid , Kent F. Knox
IPC分类号： G01R3126
CPC分类号： G01R31/2831
摘要： A method for identifying faulty wafers includes processing a set of wafers in a tool; collecting tool state information during the processing of the set of wafers; generating a tool state information baseline; comparing the tool state information for each wafer to the tool state information baseline to identify any wafers with outlying tool state information; and designating a particular wafer in the set as suspect in response to identifying outlying tool state information for the particular wafer. A processing line includes a tool adapted to process a set of wafers, and a process controller. The process controller is adapted to collect tool state information during the processing of the set of wafers, generate a tool state information baseline, compare the tool state information for each wafer to the baseline tool state information to identify any wafers with outlying tool state information, and designate a particular wafer in the set as suspect in response to identifying outlying tool state information for the particular wafer.
摘要翻译：用于识别故障晶片的方法包括在工具中处理一组晶片; 在处理该组晶片期间收集工具状态信息; 生成工具状态信息基线; 将每个晶片的工具状态信息与工具状态信息基准进行比较，以识别具有外围工具状态信息的任何晶片; 以及响应于识别用于特定晶片的外部工具状态信息而将所述组中的特定晶片指定为可疑的。处理线包括适于处理一组晶片的工具和过程控制器。过程控制器适于在晶片组的处理期间收集工具状态信息，产生工具状态信息基线，将每个晶片的工具状态信息与基准工具状态信息进行比较，以识别具有外围工具状态信息的任何晶片，并且响应于识别用于特定晶片的外部工具状态信息而将集合中的特定晶片指定为可疑。

8. 发明授权

US06629012B1 Wafer-less qualification of a processing tool 有权
标题翻译：无晶圆加工工具的资格
公开(公告)号：US06629012B1
公开(公告)日：2003-09-30
申请号：US09479403
申请日：2000-01-06
申请人： Terrence J. Riley , Qingsu Wang , Michael R. Conboy , Michael L. Miller , W. Jarrett Campbell
发明人： Terrence J. Riley , Qingsu Wang , Michael R. Conboy , Michael L. Miller , W. Jarrett Campbell
IPC分类号： G06F1900
CPC分类号： H01L21/67253 , G05B19/4184 , G05B2219/45031 , Y02P90/14 , Y02P90/22
摘要： A metbod for perforning a wafer-less qualification of a processing tool includes creating a wafer-less qualification model for the processing tool. Qualification data is generated from the processing tool iiiring a wafer-less qualification process. The qualification data is compared with the wafer-less qualification model. The processig tool is determined to be operating in a predefined state based on the comparison of the qualification data with the wafer-less qualification model.
摘要翻译：用于穿透无晶圆处理工具的资格的metbod包括为处理工具创建无晶圆的鉴定模型。资格数据是从处理工具生成的，不需要无晶圆资格认证。将资格数据与无晶圆资格认证模型进行比较。基于资格数据与无晶圆资格认证模型的比较，流程工具被确定为在预定状态下操作。

9. 发明授权

US07435651B2 Method to obtain uniform nitrogen profile in gate dielectrics 有权
标题翻译：在栅极电介质中获得均匀氮分布的方法
公开(公告)号：US07435651B2
公开(公告)日：2008-10-14
申请号：US11224219
申请日：2005-09-12
申请人： Ajith Varghese , Reima T. Laaksonen , Terrence J. Riley
发明人： Ajith Varghese , Reima T. Laaksonen , Terrence J. Riley
IPC分类号： H01L21/8234
CPC分类号： H01L21/28202 , H01L21/28194 , H01L21/823462 , H01L29/513 , H01L29/518 , Y10S438/981
摘要： The present invention, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate 115 and having a thickness less than a thickness of the first gate dielectric layer 160, and subjecting the first and second gate dielectric layers 160,165 to a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics device 100 fabricated in accordance with the method.
摘要翻译：本发明在一个方面提供了一种制造微电子器件100的方法，该方法包括在衬底115上沉积第一栅极电介质层160，对第一栅极电介质层160进行第一次氮化处理，形成第二栅极电介质层 165，并且具有小于第一栅极电介质层160的厚度的厚度，以及使第一和第二栅极电介质层160,165进行第二次氮化处理，其中第一和第二次氮化处理是不同的。本发明还提供了一种根据该方法制造的微电子器件100。

10. 发明授权

US07638402B2 Sidewall spacer pullback scheme 有权
标题翻译：侧壁间隔回拉方案
公开(公告)号：US07638402B2
公开(公告)日：2009-12-29
申请号：US11728928
申请日：2007-03-27
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Terrence J. Riley
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Terrence J. Riley
IPC分类号： H01L21/336
CPC分类号： H01L21/823468 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.
摘要翻译：在形成晶体管时实现侧壁间隔器回拉方案。除了别的以外，该方案允许晶体管的硅化物区域变得更大，或者更具有更大的表面积。较大的表面积具有较低的电阻，因此可以更精确地将电压施加到晶体管。该方案还允许使晶体管稍薄，使得在晶体管上形成的介电材料层中的空隙的形成得到减轻。这通过促进更可预测的或者其它期望的晶体管行为来缓解产量损失。

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