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1. 发明授权

US06629012B1 Wafer-less qualification of a processing tool 有权
标题翻译：无晶圆加工工具的资格
公开(公告)号：US06629012B1
公开(公告)日：2003-09-30
申请号：US09479403
申请日：2000-01-06
申请人： Terrence J. Riley , Qingsu Wang , Michael R. Conboy , Michael L. Miller , W. Jarrett Campbell
发明人： Terrence J. Riley , Qingsu Wang , Michael R. Conboy , Michael L. Miller , W. Jarrett Campbell
IPC分类号： G06F1900
CPC分类号： H01L21/67253 , G05B19/4184 , G05B2219/45031 , Y02P90/14 , Y02P90/22
摘要： A metbod for perforning a wafer-less qualification of a processing tool includes creating a wafer-less qualification model for the processing tool. Qualification data is generated from the processing tool iiiring a wafer-less qualification process. The qualification data is compared with the wafer-less qualification model. The processig tool is determined to be operating in a predefined state based on the comparison of the qualification data with the wafer-less qualification model.
摘要翻译：用于穿透无晶圆处理工具的资格的metbod包括为处理工具创建无晶圆的鉴定模型。资格数据是从处理工具生成的，不需要无晶圆资格认证。将资格数据与无晶圆资格认证模型进行比较。基于资格数据与无晶圆资格认证模型的比较，流程工具被确定为在预定状态下操作。

2. 发明授权

US06348289B1 System and method for controlling polysilicon feature critical dimension during processing 有权
标题翻译：用于控制多晶硅的系统和方法在处理过程中具有临界尺寸
公开(公告)号：US06348289B1
公开(公告)日：2002-02-19
申请号：US09366486
申请日：1999-08-03
申请人： Terri A. Couteau , W. Jarrett Campbell , Anthony Toprac
发明人： Terri A. Couteau , W. Jarrett Campbell , Anthony Toprac
IPC分类号： G03F730
CPC分类号： H01L22/20 , B25J9/1664 , G05B2219/45065 , H01L21/28123 , H01L21/32134
摘要： A method for processing a semiconductor topography is presented. In the present processing method, a semiconductor topography may be provided having a polysilicon feature arranged above a semiconductor substrate. The polysilicon feature may have an initial polysilicon feature critical dimension (CD). A chemical mixture, preferably contained in a chemical vessel, may also be provided. A polysilicon etch rate-effective attribute of the chemical mixture may be measured. Subsequently, an exposure time to the chemical mixture for the semiconductor topography may be calculated from the polysilicon etch rate-effective attribute, the initial polysilicon feature CD, and a goal polysilicon feature CD. By calculating an exposure time for the semiconductor topography in such a manner, the method preferably allows a final polysilicon feature CD to be more accurately controlled than in conventional processes.
摘要翻译：提出了一种半导体形貌的处理方法。在本处理方法中，可以提供具有布置在半导体衬底之上的多晶硅特征的半导体形貌。多晶硅特征可以具有初始多晶硅特征临界尺寸（CD）。还可以提供优选包含在化学容器中的化学混合物。可以测量化学混合物的多晶硅蚀刻速率有效属性。随后，可以从多晶硅蚀刻速率有效属性，初始多晶硅特征CD和目标多晶硅特征CD计算到用于半导体形貌的化学混合物的曝光时间。通过以这种方式计算半导体形貌的曝光时间，该方法优选地允许比常规工艺更精确地控制最终多晶硅特征CD。

3. 发明授权

US06643596B2 System and method for controlling critical dimension in a semiconductor manufacturing process 失效
公开(公告)号：US06643596B2
公开(公告)日：2003-11-04
申请号：US10017070
申请日：2001-12-13
申请人： Stacy K. Firth , W. Jarrett Campbell
发明人： Stacy K. Firth , W. Jarrett Campbell
IPC分类号： G06F1900
CPC分类号： G03F7/70558 , G03F7/70625 , G03F7/70641
摘要： A system and method for controlling critical dimension in a semiconductor manufacturing process. The system 10 controls critical dimension by altering focus and exposure settings, based on a single measured attribute (i.e., critical dimension) and on a process model equation. The system 10 further systematically varies focus and exposure settings (e.g., by introducing variable deviation values), in order to provide unique and stable solutions for parameters within the process model equation.

4. 发明授权

US06718224B2 System and method for estimating error in a manufacturing process 失效
标题翻译：用于估计制造过程中的误差的系统和方法
公开(公告)号：US06718224B2
公开(公告)日：2004-04-06
申请号：US09956550
申请日：2001-09-17
申请人： Stacy Firth , W. Jarrett Campbell
发明人： Stacy Firth , W. Jarrett Campbell
IPC分类号： G06F1900
CPC分类号： H01L21/67276 , G05B19/41875 , G05B2219/32194 , G05B2219/32203 , G05B2219/45031 , Y02P90/14 , Y02P90/22
摘要： A system and method for estimating errors within a semiconductor fabrication process. The system identifies an optimal number of error components based upon relevant context items. The system further estimates the error within the fabrication process and attributes portions of the error to each of the identified error components based upon feedback data received from the manufacturing process.
摘要翻译：一种用于估计半导体制造工艺中的误差的系统和方法。该系统基于相关的上下文项目来识别最佳数量的错误组件。该系统进一步估计制造过程中的误差，并根据从制造过程接收到的反馈数据，将误差的部分归因于每个所识别的误差分量。

5. 发明授权

US06276989B1 Method and apparatus for controlling within-wafer uniformity in chemical mechanical polishing 有权
标题翻译：用于控制化学机械抛光中晶片内均匀性的方法和装置
公开(公告)号：US06276989B1
公开(公告)日：2001-08-21
申请号：US09372014
申请日：1999-08-11
申请人： W. Jarrett Campbell , Jeremy Lansford , Christopher H. Raeder
发明人： W. Jarrett Campbell , Jeremy Lansford , Christopher H. Raeder
IPC分类号： B24B4900
CPC分类号： B24B37/005 , B24B37/042 , B24B49/03
摘要： A method of controlling surface non-uniformity of a process layer includes receiving a first lot of wafers, and polishing a process layer of the first lot of wafers. A control variable of the polishing operations is measured after the polishing is performed on the process layer. A first adjustment input for an arm oscillation length of a polishing tool is determined based on the measurement of the control variable. A process layer of a second lot of wafers is polished using the adjustment input for the arm oscillation length. A controller for controlling surface non-uniformity of a process layer includes an optimizer and an interface. The optimizer is adapted to determine a first adjustment input for arm oscillation length of a polishing tool based on a measurement of a control variable from a first lot of wafers. The interface is adapted to provide the first adjustment input to the polishing tool for polishing a second lot of wafers.
摘要翻译：控制处理层的表面不均匀性的方法包括接收第一批晶片，并抛光第一批晶片的工艺层。在对工艺层进行抛光之后，测量抛光操作的控制变量。基于控制变量的测量来确定用于抛光工具的臂振荡长度的第一调节输入。使用用于臂振荡长度的调节输入来抛光第二批晶片的处理层。用于控制处理层的表面不均匀性的控制器包括优化器和接口。优化器适于基于来自第一批晶片的控制变量的测量来确定抛光工具的臂振荡长度的第一调整输入。接口适于提供第一调整输入到抛光工具以抛光第二批晶片。

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