专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06911692B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06911692B2
公开(公告)日：2005-06-28
申请号：US10646590
申请日：2003-08-22
申请人： Takashi Kobayashi , Tatsuhiko Fujihira , Hitoshi Abe , Yasushi Niimura , Masanori Inoue
发明人： Takashi Kobayashi , Tatsuhiko Fujihira , Hitoshi Abe , Yasushi Niimura , Masanori Inoue
IPC分类号： H01L23/29 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7802 , H01L23/293 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/4238 , H01L29/7395 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A MOS semiconductor device includes n−-type surface regions, which are extended portions of an n−-type drift layer 12 extended to the surface of the semiconductor chip. Each n−-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n−-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 μm or less.
摘要翻译：一种MOS半导体器件包括n + O - 型表面区域，其是延伸到半导体芯片的表面的n + O - 型漂移层12的延伸部分。每一个n型 - 表面区域14成形为由p型阱区域围绕的条纹。包括n + +型区域15在内的n + - 型表面区域14和p型阱区域13之间的表面积比为0.01〜0.2。 MOS半导体器件在其击穿区域中进一步包括多个保护环，其数量等于或大于根据以下等式计算的数n：n =（击穿电压Vbr（V））/ 100 ，相邻保护环之间的间隔设定为1um以下。

2. 发明授权

US06943410B2 High power vertical semiconductor device 有权
标题翻译：大功率立式半导体器件
公开(公告)号：US06943410B2
公开(公告)日：2005-09-13
申请号：US10170216
申请日：2002-06-12
申请人： Tatsuhiko Fujihira , Takashi Kobayashi , Hitoshi Abe , Yasushi Niimura , Masanori Inoue
发明人： Tatsuhiko Fujihira , Takashi Kobayashi , Hitoshi Abe , Yasushi Niimura , Masanori Inoue
IPC分类号： H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L23/58
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/402 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A vertical MOS semiconductor device exhibits a high breakdown voltage and low on-resistance, reduces the tradeoff relation between the on-resistance and the breakdown voltage, and realizes high speed switching. The semiconductor device has a breakdown-voltage sustaining layer, such as an n−-type drift layer, and a well region, such as a p-type well region, in the breakdown-voltage sustaining layer. The resistivity ρ (Ωcm) of the breakdown-voltage layer is within a range expressed in terms of the breakdown voltage Vbr (V). The semiconductor device also has stripe shaped surface drain regions that extend from the well region and are surrounded by the well region. The surface area ratio between surface drain regions and the well region, which includes the source region, is from 0.01 to 0.2.
摘要翻译：垂直MOS半导体器件表现出高的击穿电压和低导通电阻，降低了导通电阻和击穿电压之间的折衷关系，实现了高速切换。该半导体器件具有击穿电压维持层，例如n + P型漂移层，以及击穿电压维持层中的诸如p型阱区的阱区。击穿电压层的电阻率rho（Ωgacm）在以击穿电压Vbr（V）表示的范围内。半导体器件还具有从阱区域延伸并被阱区域包围的条形表面漏极区域。表面漏区与包含源区的阱区的表面积比为0.01〜0.2。

3. 发明授权

US06894319B2 Semiconductor device 有权
公开(公告)号：US06894319B2
公开(公告)日：2005-05-17
申请号：US10020573
申请日：2001-10-31
申请人： Takashi Kobayashi , Tatsuhiko Fujihira , Hitoshi Abe , Yasushi Niimura , Masanori Inoue
发明人： Takashi Kobayashi , Tatsuhiko Fujihira , Hitoshi Abe , Yasushi Niimura , Masanori Inoue
IPC分类号： H01L23/29 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7802 , H01L23/293 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/4238 , H01L29/7395 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A MOS semiconductor device includes n−-type surface regions, which are extended portions of an n−-type drift layer 12 extended to the surface of the semiconductor chip. Each n−-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n−-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 μm or less.

4. 发明授权

US07911020B2 Semiconductor device having breakdown voltage maintaining structure and its manufacturing method 有权
标题翻译：具有击穿电压保持结构的半导体器件及其制造方法
公开(公告)号：US07911020B2
公开(公告)日：2011-03-22
申请号：US12171193
申请日：2008-07-10
申请人： Yasushi Niimura , Takashi Kobayashi , Masanori Inoue , Yasuhiko Onishi
发明人： Yasushi Niimura , Takashi Kobayashi , Masanori Inoue , Yasuhiko Onishi
IPC分类号： H01L29/02
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/1095 , H01L29/404 , H01L29/41741 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has an active portion having at least one well region in a semiconductor layer, and a breakdown voltage maintaining structure surrounding the active portion. The maintaining structure includes a conductor layer over each of a plurality of guard rings with an insulating film interposed in between and connected to the respective guard ring. An inner side end portion of each conductor layer projects over the immediate adjacent inner side guard ring. The impurity concentration of the guard rings is set between the impurity concentrations of the semiconductor layer and the well regions. A field plate can extend over the innermost conductor layer with the insulating film interposed in between. The field plate is in contact with the outermost well region and is in contact with the first conductor layer. The outer side end of the field plate extends outwardly beyond an outer side end of the innermost conductor layer. With these arrangements, the guard rings can be shortened and the chip size can be reduced. Furthermore, the device can be made less susceptible to external charge.
摘要翻译：半导体器件具有在半导体层中具有至少一个阱区的有源部分和围绕有源部分的击穿电压保持结构。保持结构包括在多个保护环中的每一个上的导体层，绝缘膜介于其间并连接到相应的保护环。每个导体层的内侧端部突出在紧邻的内侧保护环上。保护环的杂质浓度设定在半导体层和阱区的杂质浓度之间。场板可以在绝缘膜介于其间的最内侧的导体层上延伸。场板与最外层区域接触并与第一导体层接触。场板的外侧端部向外延伸超出最内侧导体层的外侧端部。通过这些布置，可以缩短保护环，并且可以减小芯片尺寸。此外，可以使该装置不易受到外部充电的影响。

5. 发明申请

US20050145933A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050145933A1
公开(公告)日：2005-07-07
申请号：US10973946
申请日：2004-10-26
申请人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Hitoshi Abe
发明人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Hitoshi Abe
IPC分类号： H01L29/06 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696
摘要： A semiconductor device includes an active region, an alternating conductivity type layer, and an insulation region surrounding the alternating conductivity type layer provided in a periphery section as a voltage withstanding section. The insulation region is made of an insulator with the critical electric field strength higher than that of the semiconductor and reaches an n+-drain layer on the bottom surface side of the device from a surface on the side on which a surface structure section is formed. In the alternating conductivity type layer, the width of the p-type partition region adjacent to the insulation region is made narrower than the width of the p-type partition region not adjacent to the insulation region to ensure a balanced state of charges at the end of the drift section made up of the alternating conductivity type layer. A high breakdown voltage is ensured with the length of the periphery section shortened.
摘要翻译：半导体器件包括有源区，交变导电类型层和围绕设置在周边部分中的交变导电类型层的绝缘区域作为耐压部分。绝缘区域由临界电场强度高于半导体的绝缘体制成，并从设备侧面上的表面到达器件底面侧的n + 其形成表面结构部分。在交变导电型层中，与绝缘区域相邻的p型分隔区域的宽度比不与绝缘区域相邻的p型分隔区域的宽度窄，以确保最终的电荷平衡状态由交替导电型层构成的漂移部分。确保周边部分的长度缩短的高击穿电压。

6. 发明申请

US20060033153A1 Semiconductor device with improved breakdown voltage and high current capacity 有权
标题翻译：具有改善的击穿电压和高电流容量的半导体器件
公开(公告)号：US20060033153A1
公开(公告)日：2006-02-16
申请号：US11197751
申请日：2005-08-04
申请人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Masanori Inoue
发明人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Masanori Inoue
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/7802
摘要： The superjunction semiconductor device includes a drain drift section, which includes a first alternating conductivity type layer formed of first n-type regions and first p-type regions arranged alternately. The device also includes a peripheral section around the drain drift section, which includes a second alternating conductivity type layer formed of second n-type regions and second p-type regions arranged alternately. The peripheral section further includes a third alternating conductivity type layer in its surface portion. The third alternating conductivity type layer is formed of third n-type regions and third p-type regions arranged alternately. At least the peripheral section is configured to improve the avalanche withstanding capability over the entire device.
摘要翻译：超级结半导体器件包括漏极漂移部分，其包括由第一n型区域和交替布置的第一p型区域形成的第一交变导电类型层。该装置还包括围绕漏极漂移部分的周边部分，其包括由交替布置的第二n型区域和第二p型区域形成的第二交变导电类型层。外围部分还包括在其表面部分中的第三交变导电类型层。第三交变导电型层由交替布置的第三n型区域和第三p型区域形成。至少外围部分被配置为提高整个设备上的雪崩承受能力。

7. 发明授权

US07235841B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07235841B2
公开(公告)日：2007-06-26
申请号：US10973946
申请日：2004-10-26
申请人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Hitoshi Abe
发明人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Hitoshi Abe
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L29/00
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696
摘要： A semiconductor device includes an active region, an alternating conductivity type layer, and an insulation region surrounding the alternating conductivity type layer provided in a periphery section as a voltage withstanding section. The insulation region is made of an insulator with the critical electric field strength higher than that of the semiconductor and reaches an n+-drain layer on the bottom surface side of the device from a surface on the side on which a surface structure section is formed. In the alternating conductivity type layer, the width of the p-type partition region adjacent to the insulation region is made narrower than the width of the p-type partition region not adjacent to the insulation region to ensure a balanced state of charges at the end of the drift section made up of the alternating conductivity type layer. A high breakdown voltage is ensured with the length of the periphery section shortened.
摘要翻译：半导体器件包括有源区，交变导电类型层和围绕设置在周边部分中的交变导电类型层的绝缘区域作为耐压部分。绝缘区域由临界电场强度高于半导体的绝缘体制成，并从设备侧面上的表面到达器件底面侧的n + 其形成表面结构部分。在交变导电型层中，与绝缘区域相邻的p型分隔区域的宽度比不与绝缘区域相邻的p型分隔区域的宽度窄，以确保最终的电荷平衡状态由交替导电型层构成的漂移部分。确保周边部分的长度缩短的高击穿电压。

8. 发明授权

US07372111B2 Semiconductor device with improved breakdown voltage and high current capacity 有权
标题翻译：具有改善的击穿电压和高电流容量的半导体器件
公开(公告)号：US07372111B2
公开(公告)日：2008-05-13
申请号：US11197751
申请日：2005-08-04
申请人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Masanori Inoue
发明人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Masanori Inoue
IPC分类号： H01L29/72
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/7802
摘要： The superjunction semiconductor device includes a drain drift section, which includes a first alternating conductivity type layer formed of first n-type regions and first p-type regions arranged alternately. The device also includes a peripheral section around the drain drift section, which includes a second alternating conductivity type layer formed of second n-type regions and second p-type regions arranged alternately. The peripheral section further includes a third alternating conductivity type layer in its surface portion. The third alternating conductivity type layer is formed of third n-type regions and third p-type regions arranged alternately. At least the peripheral section is configured to improve the avalanche withstanding capability over the entire device.
摘要翻译：超级结半导体器件包括漏极漂移部分，其包括由第一n型区域和交替布置的第一p型区域形成的第一交变导电类型层。该装置还包括围绕漏极漂移部分的周边部分，其包括由交替布置的第二n型区域和第二p型区域形成的第二交变导电类型层。外围部分还包括在其表面部分中的第三交变导电类型层。第三交变导电型层由交替布置的第三n型区域和第三p型区域形成。至少外围部分被配置为提高整个设备上的雪崩承受能力。

9. 发明授权

US07859083B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07859083B2
公开(公告)日：2010-12-28
申请号：US12188627
申请日：2008-08-08
申请人： Takeyoshi Nishimura , Takashi Kobayashi , Yasushi Niimura , Tadanori Yamada
发明人： Takeyoshi Nishimura , Takashi Kobayashi , Yasushi Niimura , Tadanori Yamada
IPC分类号： H01L29/861 , H03K17/74
CPC分类号： H01L27/0629 , H01L27/0255 , H01L29/0696 , H01L29/7808 , H01L29/7811 , H01L29/866
摘要： A semiconductor device is provided with Zener diodes which are formed by using a polysilicon gate layer(s) so as to be connected to each other in parallel. Parallel-connected rectangular Zener diodes are formed outside an active region or parallel-connected striped Zener diodes are formed inside the active region. The Zener diodes increase the ESD capability of the semiconductor device.
摘要翻译：半导体器件设置有通过使用多晶硅栅极层并联连接而形成的齐纳二极管。平行连接的矩形齐纳二极管形成在有源区域之外，或者在有源区域内形成并联连接的条形齐纳二极管。齐纳二极管增加了半导体器件的ESD能力。

10. 发明申请

US20120139036A1 MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS 有权
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20120139036A1
公开(公告)日：2012-06-07
申请号：US13320211
申请日：2010-07-29
申请人： Yasushi Niimura , Sota Watanabe , Hidenori Takahashi , Takumi Fujimoto , Takeyoshi Nishimura , Takamasa Wakabayashi
发明人： Yasushi Niimura , Sota Watanabe , Hidenori Takahashi , Takumi Fujimoto , Takeyoshi Nishimura , Takamasa Wakabayashi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/404 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/66712 , H01L29/66727 , H01L29/7395 , H01L29/7802
摘要： A screen oxide film is formed on an n− drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed. N-type impurity ions at a concentration higher than that of the n− drift layer are implanted through the nitride shielding film (61) from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer (7) is formed. The screen oxide film is removed. A gate oxide film (3a) is formed. A gate electrode (9) is formed on the gate oxide film (3a). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, p− well regions (10) are formed. N-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, n source regions (11) are formed.
摘要翻译：在设置在n型低电阻层（1）的前侧的n漂移层（2）上形成荧光体氧化膜，在该荧光体氧化膜上形成氮化膜。使用第一掩模对氮化物膜进行光蚀刻，从而形成氮化物屏蔽膜（61）。浓度高于n-漂移层的N型杂质离子从半导体衬底的前侧通过氮化物屏蔽膜（61）注入并被散热，从而n对准层（7）为形成。去除屏幕氧化膜。形成栅氧化膜（3a）。栅电极（9）形成在栅氧化膜（3a）上。使用栅电极（9）和氮化物屏蔽膜（61）作为掩模，从半导体衬底的前侧注入P型杂质离子，从而形成p-阱区（10）。使用栅电极（9）和氮化物屏蔽膜（61）作为掩模，从半导体衬底的前侧注入N型杂质离子，从而形成n个源区（11）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式