专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07859083B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07859083B2
公开(公告)日：2010-12-28
申请号：US12188627
申请日：2008-08-08
申请人： Takeyoshi Nishimura , Takashi Kobayashi , Yasushi Niimura , Tadanori Yamada
发明人： Takeyoshi Nishimura , Takashi Kobayashi , Yasushi Niimura , Tadanori Yamada
IPC分类号： H01L29/861 , H03K17/74
CPC分类号： H01L27/0629 , H01L27/0255 , H01L29/0696 , H01L29/7808 , H01L29/7811 , H01L29/866
摘要： A semiconductor device is provided with Zener diodes which are formed by using a polysilicon gate layer(s) so as to be connected to each other in parallel. Parallel-connected rectangular Zener diodes are formed outside an active region or parallel-connected striped Zener diodes are formed inside the active region. The Zener diodes increase the ESD capability of the semiconductor device.
摘要翻译：半导体器件设置有通过使用多晶硅栅极层并联连接而形成的齐纳二极管。平行连接的矩形齐纳二极管形成在有源区域之外，或者在有源区域内形成并联连接的条形齐纳二极管。齐纳二极管增加了半导体器件的ESD能力。

2. 发明申请

US20120139036A1 MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS 有权
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20120139036A1
公开(公告)日：2012-06-07
申请号：US13320211
申请日：2010-07-29
申请人： Yasushi Niimura , Sota Watanabe , Hidenori Takahashi , Takumi Fujimoto , Takeyoshi Nishimura , Takamasa Wakabayashi
发明人： Yasushi Niimura , Sota Watanabe , Hidenori Takahashi , Takumi Fujimoto , Takeyoshi Nishimura , Takamasa Wakabayashi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/404 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/66712 , H01L29/66727 , H01L29/7395 , H01L29/7802
摘要： A screen oxide film is formed on an n− drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed. N-type impurity ions at a concentration higher than that of the n− drift layer are implanted through the nitride shielding film (61) from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer (7) is formed. The screen oxide film is removed. A gate oxide film (3a) is formed. A gate electrode (9) is formed on the gate oxide film (3a). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, p− well regions (10) are formed. N-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, n source regions (11) are formed.
摘要翻译：在设置在n型低电阻层（1）的前侧的n漂移层（2）上形成荧光体氧化膜，在该荧光体氧化膜上形成氮化膜。使用第一掩模对氮化物膜进行光蚀刻，从而形成氮化物屏蔽膜（61）。浓度高于n-漂移层的N型杂质离子从半导体衬底的前侧通过氮化物屏蔽膜（61）注入并被散热，从而n对准层（7）为形成。去除屏幕氧化膜。形成栅氧化膜（3a）。栅电极（9）形成在栅氧化膜（3a）上。使用栅电极（9）和氮化物屏蔽膜（61）作为掩模，从半导体衬底的前侧注入P型杂质离子，从而形成p-阱区（10）。使用栅电极（9）和氮化物屏蔽膜（61）作为掩模，从半导体衬底的前侧注入N型杂质离子，从而形成n个源区（11）。

3. 发明授权

US09136352B2 Manufacturing method of semiconductor apparatus and semiconductor apparatus 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US09136352B2
公开(公告)日：2015-09-15
申请号：US13320211
申请日：2010-07-29
申请人： Yasushi Niimura , Sota Watanabe , Hidenori Takahashi , Takumi Fujimoto , Takeyoshi Nishimura , Takamasa Wakabayashi
发明人： Yasushi Niimura , Sota Watanabe , Hidenori Takahashi , Takumi Fujimoto , Takeyoshi Nishimura , Takamasa Wakabayashi
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/423
CPC分类号： H01L29/7811 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/404 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/66712 , H01L29/66727 , H01L29/7395 , H01L29/7802
摘要： A screen oxide film is formed on an n− drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed. N-type impurity ions at a concentration higher than that of the n-drift layer are implanted through the nitride shielding film (61) from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer (7) is formed. The screen oxide film is removed. A gate oxide film (3a) is formed. A gate electrode (9) is formed on the gate oxide film (3a). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, p− well regions (10) are formed. N-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, n source regions (11) are formed.
摘要翻译：在设置在n型低电阻层（1）的前侧的n漂移层（2）上形成荧光体氧化膜，在该荧光体氧化膜上形成氮化膜。使用第一掩模对氮化物膜进行光蚀刻，从而形成氮化物屏蔽膜（61）。浓度高于n漂移层的N型杂质离子从半导体衬底的前侧通过氮化物屏蔽膜（61）注入并被热扩散，由此n对置层（7）为形成。去除屏幕氧化膜。形成栅氧化膜（3a）。栅电极（9）形成在栅氧化膜（3a）上。使用栅电极（9）和氮化物屏蔽膜（61）作为掩模，从半导体衬底的前侧注入P型杂质离子，从而形成p-阱区（10）。使用栅电极（9）和氮化物屏蔽膜（61）作为掩模，从半导体衬底的前侧注入N型杂质离子，从而形成n个源区（11）。

4. 发明授权

US07372111B2 Semiconductor device with improved breakdown voltage and high current capacity 有权
标题翻译：具有改善的击穿电压和高电流容量的半导体器件
公开(公告)号：US07372111B2
公开(公告)日：2008-05-13
申请号：US11197751
申请日：2005-08-04
申请人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Masanori Inoue
发明人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Masanori Inoue
IPC分类号： H01L29/72
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/7802
摘要： The superjunction semiconductor device includes a drain drift section, which includes a first alternating conductivity type layer formed of first n-type regions and first p-type regions arranged alternately. The device also includes a peripheral section around the drain drift section, which includes a second alternating conductivity type layer formed of second n-type regions and second p-type regions arranged alternately. The peripheral section further includes a third alternating conductivity type layer in its surface portion. The third alternating conductivity type layer is formed of third n-type regions and third p-type regions arranged alternately. At least the peripheral section is configured to improve the avalanche withstanding capability over the entire device.
摘要翻译：超级结半导体器件包括漏极漂移部分，其包括由第一n型区域和交替布置的第一p型区域形成的第一交变导电类型层。该装置还包括围绕漏极漂移部分的周边部分，其包括由交替布置的第二n型区域和第二p型区域形成的第二交变导电类型层。外围部分还包括在其表面部分中的第三交变导电类型层。第三交变导电型层由交替布置的第三n型区域和第三p型区域形成。至少外围部分被配置为提高整个设备上的雪崩承受能力。

5. 发明授权

US07235841B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07235841B2
公开(公告)日：2007-06-26
申请号：US10973946
申请日：2004-10-26
申请人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Hitoshi Abe
发明人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Hitoshi Abe
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L29/00
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696
摘要： A semiconductor device includes an active region, an alternating conductivity type layer, and an insulation region surrounding the alternating conductivity type layer provided in a periphery section as a voltage withstanding section. The insulation region is made of an insulator with the critical electric field strength higher than that of the semiconductor and reaches an n+-drain layer on the bottom surface side of the device from a surface on the side on which a surface structure section is formed. In the alternating conductivity type layer, the width of the p-type partition region adjacent to the insulation region is made narrower than the width of the p-type partition region not adjacent to the insulation region to ensure a balanced state of charges at the end of the drift section made up of the alternating conductivity type layer. A high breakdown voltage is ensured with the length of the periphery section shortened.
摘要翻译：半导体器件包括有源区，交变导电类型层和围绕设置在周边部分中的交变导电类型层的绝缘区域作为耐压部分。绝缘区域由临界电场强度高于半导体的绝缘体制成，并从设备侧面上的表面到达器件底面侧的n + 其形成表面结构部分。在交变导电型层中，与绝缘区域相邻的p型分隔区域的宽度比不与绝缘区域相邻的p型分隔区域的宽度窄，以确保最终的电荷平衡状态由交替导电型层构成的漂移部分。确保周边部分的长度缩短的高击穿电压。

6. 发明申请

US20060033153A1 Semiconductor device with improved breakdown voltage and high current capacity 有权
标题翻译：具有改善的击穿电压和高电流容量的半导体器件
公开(公告)号：US20060033153A1
公开(公告)日：2006-02-16
申请号：US11197751
申请日：2005-08-04
申请人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Masanori Inoue
发明人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Masanori Inoue
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/7802
摘要： The superjunction semiconductor device includes a drain drift section, which includes a first alternating conductivity type layer formed of first n-type regions and first p-type regions arranged alternately. The device also includes a peripheral section around the drain drift section, which includes a second alternating conductivity type layer formed of second n-type regions and second p-type regions arranged alternately. The peripheral section further includes a third alternating conductivity type layer in its surface portion. The third alternating conductivity type layer is formed of third n-type regions and third p-type regions arranged alternately. At least the peripheral section is configured to improve the avalanche withstanding capability over the entire device.
摘要翻译：超级结半导体器件包括漏极漂移部分，其包括由第一n型区域和交替布置的第一p型区域形成的第一交变导电类型层。该装置还包括围绕漏极漂移部分的周边部分，其包括由交替布置的第二n型区域和第二p型区域形成的第二交变导电类型层。外围部分还包括在其表面部分中的第三交变导电类型层。第三交变导电型层由交替布置的第三n型区域和第三p型区域形成。至少外围部分被配置为提高整个设备上的雪崩承受能力。

7. 发明申请

US20050145933A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050145933A1
公开(公告)日：2005-07-07
申请号：US10973946
申请日：2004-10-26
申请人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Hitoshi Abe
发明人： Yasuhiko Onishi , Takeyoshi Nishimura , Yasushi Niimura , Hitoshi Abe
IPC分类号： H01L29/06 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696
摘要： A semiconductor device includes an active region, an alternating conductivity type layer, and an insulation region surrounding the alternating conductivity type layer provided in a periphery section as a voltage withstanding section. The insulation region is made of an insulator with the critical electric field strength higher than that of the semiconductor and reaches an n+-drain layer on the bottom surface side of the device from a surface on the side on which a surface structure section is formed. In the alternating conductivity type layer, the width of the p-type partition region adjacent to the insulation region is made narrower than the width of the p-type partition region not adjacent to the insulation region to ensure a balanced state of charges at the end of the drift section made up of the alternating conductivity type layer. A high breakdown voltage is ensured with the length of the periphery section shortened.
摘要翻译：半导体器件包括有源区，交变导电类型层和围绕设置在周边部分中的交变导电类型层的绝缘区域作为耐压部分。绝缘区域由临界电场强度高于半导体的绝缘体制成，并从设备侧面上的表面到达器件底面侧的n + 其形成表面结构部分。在交变导电型层中，与绝缘区域相邻的p型分隔区域的宽度比不与绝缘区域相邻的p型分隔区域的宽度窄，以确保最终的电荷平衡状态由交替导电型层构成的漂移部分。确保周边部分的长度缩短的高击穿电压。

8. 发明授权

US06246092B1 High breakdown voltage MOS semiconductor apparatus 失效
标题翻译：高耐压型MOS半导体装置
公开(公告)号：US06246092B1
公开(公告)日：2001-06-12
申请号：US09042544
申请日：1998-03-17
申请人： Tatsuhiko Fujihira , Takeyoshi Nishimura , Takashi Kobayashi
发明人： Tatsuhiko Fujihira , Takeyoshi Nishimura , Takashi Kobayashi
IPC分类号： H03K1728
CPC分类号： H01L29/7808 , H01L27/0248 , H01L27/0629 , H01L29/402 , H01L29/7811 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A MOS type semiconductor apparatus is provided that includes a first MOS type semiconductor device through which main current flows, and a second MOS type semiconductor device through which current that is smaller than the main current flows. The first and second MOS type semiconductor devices provided on the same semiconductor substrate have substantially the same structure, and have a common drain electrode. A gate electrode of the second MOS type semiconductor device is connected to the common drain electrode. The semiconductor apparatus further includes a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device. Each pair of Zener diodes are reversely connected to each other.
摘要翻译：提供一种MOS型半导体装置，其包括主电流流过的第一MOS型半导体器件和小于主电流的电流流过的第二MOS型半导体器件。设置在同一半导体衬底上的第一和第二MOS型半导体器件具有基本上相同的结构，并且具有公共漏电极。第二MOS型半导体器件的栅电极连接到公共漏电极。半导体装置还包括串联连接并设置在第二MOS型半导体器件的源电极和第一MOS型半导体器件的栅电极之间的多对齐纳二极管。每对齐纳二极管彼此反向连接。

9. 发明授权

US5869372A Method of manufacturing a power semiconductor device 失效
标题翻译：制造功率半导体器件的方法
公开(公告)号：US5869372A
公开(公告)日：1999-02-09
申请号：US555426
申请日：1995-11-09
申请人： Tatsuhiko Fujihira , Seiji Momota , Takeyoshi Nishimura , Kazutoshi Sugimura , Masao Yoshino , Takashi Kobayashi
发明人： Tatsuhiko Fujihira , Seiji Momota , Takeyoshi Nishimura , Kazutoshi Sugimura , Masao Yoshino , Takashi Kobayashi
IPC分类号： H01L21/28 , H01L21/265 , H01L21/266 , H01L21/306 , H01L21/316 , H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823857 , H01L21/266
摘要： A semiconductor device manufacturing process is disclosed in which one processing step is reduced by replacing the photoresist film conventionally used for masking in the formation of the heavily doped n-type layer by an oxide film, and by monitoring, in the monitor region, the simultaneous formation of the contact holes in the oxide films different in the respective thickness thereof. An n+ region is formed by using a second insulation film and a polysilicon gate electrode formed on a semi-conductor wafer as masks for implanting arsenic ions. Further, a contact hole to be formed on a p-type region covered with a fourth insulation film and a second insulation film and a contact hole to be formed on the n+ region covered with the fourth insulation film are formed simultaneously under the monitoring of the formation of the contact holes in a monitor region.
摘要翻译：公开了一种半导体器件制造方法，其中通过用氧化膜替代常规用于形成重掺杂n型层的掩模的光致抗蚀剂膜，并且通过在监测区域中监测同时形成不同厚度的氧化膜中的接触孔。通过使用形成在半导体晶片上的第二绝缘膜和多晶硅栅极作为用于注入砷离子的掩模来形成n +区。此外，在被覆有第四绝缘膜的p型区域上形成的接触孔和被覆有第四绝缘膜的n +区域上形成的第二绝缘膜和接触孔同时形成在在监视器区域中形成接触孔。

10. 发明授权

US06548865B2 High breakdown voltage MOS type semiconductor apparatus 有权
标题翻译：高耐压MOS型半导体装置
公开(公告)号：US06548865B2
公开(公告)日：2003-04-15
申请号：US09799430
申请日：2001-03-05
申请人： Tatsuhiko Fujihira , Takeyoshi Nishimura , Takashi Kobayashi
发明人： Tatsuhiko Fujihira , Takeyoshi Nishimura , Takashi Kobayashi
IPC分类号： H01L2976
CPC分类号： H01L29/7808 , H01L27/0248 , H01L27/0629 , H01L29/402 , H01L29/7811 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A MOS type semiconductor apparatus is provided that includes a first MOS type semiconductor device through which main current flows, and a second MOS type semiconductor device through which current that is smaller than the main current flows. The first and second MOS type semiconductor devices provided on the same semiconductor substrate have substantially the same structure, and have a common drain electrode. A gate electrode of the second MOS type semiconductor device is connected to the common drain electrode. The semiconductor apparatus further includes a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device. Each pair of Zener diodes are reversely connected to each other.
摘要翻译：提供一种MOS型半导体装置，其包括主电流流过的第一MOS型半导体器件和小于主电流的电流流过的第二MOS型半导体器件。设置在同一半导体衬底上的第一和第二MOS型半导体器件具有基本上相同的结构，并且具有公共漏电极。第二MOS型半导体器件的栅电极连接到公共漏电极。半导体装置还包括串联连接并设置在第二MOS型半导体器件的源电极和第一MOS型半导体器件的栅电极之间的多对齐纳二极管。每对齐纳二极管彼此反向连接。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式