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1. 发明授权

US06383938B2 Method of anisotropic etching of substrates 有权
标题翻译：基板各向异性蚀刻方法
公开(公告)号：US06383938B2
公开(公告)日：2002-05-07
申请号：US09295100
申请日：1999-04-21
申请人： Tamarak Pandhumsoporn , Kevin Yu , Michael Feldbaum , Michel Puech
发明人： Tamarak Pandhumsoporn , Kevin Yu , Michael Feldbaum , Michel Puech
IPC分类号： H01L21302
CPC分类号： H01L21/30655
摘要： A method of plasma etching of silicon that utilizes the plasma to provide laterally defined recess structures through a mask. The method is based on the variation of the plasma parameters to provide a well-controlled anisotropic etch, while achieving a very high etch rate, and a high selectivity with respect to a mask. A mixed gas is introduced into the vacuum chamber after the chamber is evacuated, and plasma is generated within the chamber. The substrate's surface is exposed to the plasma. Power sources are used for formation of the plasma discharge. An integrated control system is used to modulate the plasma discharge power and substrate polarization voltage levels.
摘要翻译：利用等离子体通过掩模提供横向限定的凹陷结构的等离子体蚀刻硅的方法。该方法基于等离子体参数的变化，以提供良好控制的各向异性蚀刻，同时实现非常高的蚀刻速率和相对于掩模的高选择性。在室抽真空之后，将混合气体引入真空室中，并且在室内产生等离子体。衬底的表面暴露于等离子体。电源用于形成等离子体放电。使用集成控制系统来调制等离子体放电功率和衬底极化电压电平。

2. 发明申请

US20060131271A1 Methods and apparatus for sequentially alternating among plasma processes in order to optimize a substrate 有权
标题翻译：在等离子体工艺中顺序交替的方法和装置，以便优化衬底
公开(公告)号：US20060131271A1
公开(公告)日：2006-06-22
申请号：US11022983
申请日：2004-12-22
申请人： Adrian Kiermasz , Tamarak Pandhumsoporn , Alferd Cofer
发明人： Adrian Kiermasz , Tamarak Pandhumsoporn , Alferd Cofer
IPC分类号： C23F1/00
CPC分类号： C03C23/006 , C23C4/02 , H01J37/32935 , H01L21/67253
摘要： In a plasma processing system, a method for optimizing etching of a substrate is disclosed. The method includes selecting a first plasma process recipe including a first process variable, wherein changing the first process variable by a first amount optimizes a first substrate etch characteristic and aggravates a second substrate etch characteristic. The method also includes selecting second plasma process recipe including a second process variable, wherein changing the second process variable by a second amount aggravates the first substrate etch characteristic and optimizes the second substrate etch characteristic. The method further includes positioning a substrate on a chuck in a plasma processing chamber; and striking a plasma within the plasma processing chamber. The method also includes alternating between the first plasma recipe and the second plasma recipe, wherein upon completion of the alternating, the first substrate etch characteristic and the second substrate etch characteristic are substantially optimized.
摘要翻译：在等离子体处理系统中，公开了一种用于优化衬底蚀刻的方法。该方法包括选择包括第一过程变量的第一等离子体处理配方，其中以第一量改变第一过程变量优化第一衬底蚀刻特性并加重第二衬底蚀刻特性。该方法还包括选择包括第二过程变量的第二等离子体处理配方，其中以第二量改变第二过程变量加剧了第一衬底蚀刻特性并优化了第二衬底蚀刻特性。该方法还包括将基板定位在等离子体处理室中的卡盘上; 并在等离子体处理室内击打等离子体。该方法还包括在第一等离子体配方和第二等离子体配方之间交替，其中在完成交替时，基本上优化了第一衬底蚀刻特性和第二衬底蚀刻特性。

3. 发明授权

US07985688B2 Notch stop pulsing process for plasma processing system 有权
标题翻译：等离子体处理系统的停止脉冲过程
公开(公告)号：US07985688B2
公开(公告)日：2011-07-26
申请号：US11305440
申请日：2005-12-16
申请人： Tamarak Pandhumsoporn , Alferd Cofer
发明人： Tamarak Pandhumsoporn , Alferd Cofer
IPC分类号： H01L21/302
CPC分类号： H01L21/30655
摘要： A method for etching a substrate having a silicon layer in a plasma processing chamber having a bottom electrode on which the substrate is disposed on during etching. The method includes performing a main etch step. The method also includes terminating main etch step when a predefined etch depth of at least 70 percent of thickness into silicon layer is achieved. The method further includes performing an overetch step. The overetch step including a first process step and a second process step. First process step is performed using a first bottom power level applied to bottom electrode. Second process step is performed using a second bottom power level applied to bottom electrode that is lower than first bottom power level. First process and second process steps are alternately performed a plurality of times. The method yet also includes terminating overetch step after silicon layer is etched through.
摘要翻译：一种用于在蚀刻期间蚀刻具有底层电极的等离子体处理室中具有硅层的衬底的方法。该方法包括执行主蚀刻步骤。当达到至少70％的厚度的预定蚀刻深度达到硅层时，该方法还包括终止主蚀刻步骤。所述方法还包括执行过程延展步骤。该疏水步骤包括第一工艺步骤和第二工艺步骤。使用施加到底部电极的第一底部功率电平来执行第一处理步骤。使用低于第一底部功率电平的施加到底部电极的第二底部功率电平来执行第二工艺步骤。交替执行第一处理和第二处理步骤多次。该方法还包括在蚀刻硅层之后终止过蚀刻步骤。

4. 发明授权

US07459100B2 Methods and apparatus for sequentially alternating among plasma processes in order to optimize a substrate 有权
标题翻译：在等离子体工艺中顺序交替的方法和装置，以便优化衬底
公开(公告)号：US07459100B2
公开(公告)日：2008-12-02
申请号：US11022983
申请日：2004-12-22
申请人： Adrian Kiermasz , Tamarak Pandhumsoporn , Alferd Cofer
发明人： Adrian Kiermasz , Tamarak Pandhumsoporn , Alferd Cofer
IPC分类号： C23F1/00
CPC分类号： C03C23/006 , C23C4/02 , H01J37/32935 , H01L21/67253
摘要： In a plasma processing system, a method for optimizing etching of a substrate is disclosed. The method includes selecting a first plasma process recipe including a first process variable, wherein changing the first process variable by a first amount optimizes a first substrate etch characteristic and aggravates a second substrate etch characteristic. The method also includes selecting second plasma process recipe including a second process variable, wherein changing the second process variable by a second amount aggravates the first substrate etch characteristic and optimizes the second substrate etch characteristic. The method further includes positioning a substrate on a chuck in a plasma processing chamber; and striking a plasma within the plasma processing chamber. The method also includes alternating between the first plasma recipe and the second plasma recipe, wherein upon completion of the alternating, the first substrate etch characteristic and the second substrate etch characteristic are substantially optimized.
摘要翻译：在等离子体处理系统中，公开了一种用于优化衬底蚀刻的方法。该方法包括选择包括第一过程变量的第一等离子体处理配方，其中以第一量改变第一过程变量优化第一衬底蚀刻特性并加重第二衬底蚀刻特性。该方法还包括选择包括第二过程变量的第二等离子体处理配方，其中以第二量改变第二过程变量加剧了第一衬底蚀刻特性并优化了第二衬底蚀刻特性。该方法还包括将基板定位在等离子体处理室中的卡盘上; 并在等离子体处理室内击打等离子体。该方法还包括在第一等离子体配方和第二等离子体配方之间交替，其中在完成交替时，基本上优化了第一衬底蚀刻特性和第二衬底蚀刻特性。

5. 发明申请

US20050211668A1 Methods of processing a substrate with minimal scalloping 审中-公开
标题翻译：以最小的扇贝处理基材的方法
公开(公告)号：US20050211668A1
公开(公告)日：2005-09-29
申请号：US10882036
申请日：2004-06-29
申请人： Tamarak Pandhumsoporn
发明人： Tamarak Pandhumsoporn
IPC分类号： B44C1/22 , H01L21/302 , H01L21/3065
CPC分类号： H01L21/30655
摘要： The present invention provides methods of processing a substrate with minimal scalloping. By processing substrates with minimal scalloping, feature tolerance and quality may be improved. An embodiment of the present invention provides a method for etching a feature in a layer through an etching mask by alternating steps of polymer deposition and substrate etching in any order. In order to achieve the benefits described herein, process gas pressures between process steps may be substantially equivalent. In some embodiments a continuous plasma stream may be maintained throughout substrate processing. In still other embodiments, process gases may be controlled by a single mass flow control valve so that process gases may be switched to within less than 250 milliseconds.
摘要翻译：本发明提供了以最小的扇贝处理衬底的方法。通过以最小的扇贝处理基板，可以提高特征公差和质量。本发明的一个实施例提供了通过聚合物沉积和基板蚀刻的任意顺序的交替步骤通过蚀刻掩模蚀刻层中的特征的方法。为了实现本文所述的优点，工艺步骤之间的工艺气体压力可以是基本相当的。在一些实施方案中，可以在整个基板处理中维持连续的等离子体流。在其它实施例中，处理气体可以由单个质量流量控制阀控制，使得处理气体可以在不到250毫秒内切换。

6. 发明授权

US08262920B2 Minimization of mask undercut on deep silicon etch 有权
标题翻译：在深硅蚀刻上最小化掩模底切
公开(公告)号：US08262920B2
公开(公告)日：2012-09-11
申请号：US11820334
申请日：2007-06-18
申请人： Tamarak Pandhumsoporn , Patrick Chung , Jackie Seto , S. M. Reza Sadjadi
发明人： Tamarak Pandhumsoporn , Patrick Chung , Jackie Seto , S. M. Reza Sadjadi
IPC分类号： C03C15/00
CPC分类号： H01L21/3086 , H01L21/31138
摘要： A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C4F8, forming a plasma from the deposition gas, depositing a polymer from the plasma for at least 20 seconds, and stopping the depositing the polymer after the at least 20 seconds. The deposited polymer layer is opened by flowing an opening gas, forming a plasma from the opening gas which selectively removes the deposited polymer on bottoms of the plurality of mask openings with respect to deposited polymer on sides of the plurality of mask openings, and stopping the opening when at least some of the plurality of mask features are opened. The silicon layer is etched through the mask and deposited polymer layer.
摘要翻译：提供了一种在硅层中形成特征的方法。在硅层上形成有多个掩模开口的掩模。通过使包含C4F8的无氢沉积气体从沉积气体形成等离子体，从等离子体沉积聚合物至少20秒，并在至少20秒后停止沉积聚合物，沉积聚合物层。沉积的聚合物层通过流动开口气体而打开，从开口气体形成等离子体，其在多个掩模开口的侧面上相对于沉积的聚合物选择性地去除多个掩模开口的底部上沉积的聚合物，并且停止当多个掩模特征中的至少一些被打开时打开。通过掩模蚀刻硅层并沉积聚合物层。

7. 发明授权

US07351664B2 Methods for minimizing mask undercuts and notches for plasma processing system 有权
标题翻译：用于最小化等离子体处理系统的掩模底切和凹口的方法
公开(公告)号：US07351664B2
公开(公告)日：2008-04-01
申请号：US11421000
申请日：2006-05-30
申请人： Tamarak Pandhumsoporn , Alferd Cofer , William Bosch
发明人： Tamarak Pandhumsoporn , Alferd Cofer , William Bosch
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/30655 , B81C1/00571 , H01L21/32137
摘要： A method for etching silicon layer of a substrate, which is deposited on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of silicon layer is etched. The method further includes an overetch step, which includes a first, second, and third process steps. The first process step employs a first process recipe, the second process step employs a second process recipe, and the third process step employs a third process recipe. The second process recipe employs a second bottom bias voltage level applied to the bottom electrode which is higher than the first bottom bias voltage level employs in the first process recipe and the third bottom bias voltage level employs in the third process recipe. The first, second, and third process steps are alternated a plurality of times until silicon layer is etched through.
摘要翻译：一种用于蚀刻沉积在等离子体处理室中的底部电极上的衬底的硅层的方法。该方法包括执行主蚀刻步骤，直到至少70％的硅层被蚀刻。该方法还包括一个过程延伸步骤，其包括第一，第二和第三工艺步骤。第一处理步骤采用第一处理配方，第二处理步骤采用第二处理配方，并且第三处理步骤采用第三处理配方。第二工艺配方采用施加到底部电极的第二底部偏置电压电平，该第二底部偏置电压电平高于第一工艺配方中使用的第一底部偏置电压电平，而第三工艺配方中采用第三底部偏置电压电平。第一，第二和第三工艺步骤交替多次，直到硅层被蚀刻通过。

8. 发明授权

US06287437B1 Recessed bonding of target for RF diode sputtering 失效
标题翻译：用于RF二极管溅射的靶的凹入结合
公开(公告)号：US06287437B1
公开(公告)日：2001-09-11
申请号：US09564582
申请日：2000-05-05
申请人： Tamarak Pandhumsoporn , Mark Feldman
发明人： Tamarak Pandhumsoporn , Mark Feldman
IPC分类号： C23C1434
CPC分类号： C23C14/3407
摘要： A recessed sputtering target assembly is provided with a bonding material disposed between a dielectric target and a backing plate. The bond line of the bonding material is recessed away from the edges of the target and backing plate, preferably by ¼ inch. The sputtering target assembly may be used during high RF power processes to achieve high deposition rates without arcing of the bonding material or contamination of the sputtering chamber.
摘要翻译：凹陷式溅射靶组件设置有设置在电介质靶和背板之间的接合材料。接合材料的接合线从目标和背板的边缘凹进，优选地为1/4英寸。可以在高RF功率工艺期间使用溅射靶组件，以实现高沉积速率，而不会引起接合材料的电弧或溅射室的污染。

9. 发明申请

US20120298301A1 MINIMIZATION OF MASK UNDERCUT ON DEEP ETCH 审中-公开
标题翻译：深层蚀刻掩蔽最小化
公开(公告)号：US20120298301A1
公开(公告)日：2012-11-29
申请号：US13572061
申请日：2012-08-10
申请人： Tamarak Pandhumsoporn , Patrick Chung , Jackie Seto , S. M. Reza Sadjadi
发明人： Tamarak Pandhumsoporn , Patrick Chung , Jackie Seto , S. M. Reza Sadjadi
IPC分类号： C23F1/08
CPC分类号： H01L21/3086 , H01L21/31138
摘要： A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C4F8, forming a plasma from the deposition gas, depositing a polymer from the plasma for at least 20 seconds, and stopping the depositing the polymer after the at least 20 seconds. The deposited polymer layer is opened by flowing an opening gas, forming a plasma from the opening gas which selectively removes the deposited polymer on bottoms of the plurality of mask openings with respect to deposited polymer on sides of the plurality of mask openings, and stopping the opening when at least some of the plurality of mask features are opened. The silicon layer is etched through the mask and deposited polymer layer.
摘要翻译：提供了一种在硅层中形成特征的方法。在硅层上形成有多个掩模开口的掩模。通过使包含C4F8的无氢沉积气体从沉积气体形成等离子体，从等离子体沉积聚合物至少20秒，并在至少20秒后停止沉积聚合物，沉积聚合物层。沉积的聚合物层通过流动开口气体而打开，从开口气体形成等离子体，其在多个掩模开口的侧面上相对于沉积的聚合物选择性地去除多个掩模开口的底部上沉积的聚合物，并且停止当多个掩模特征中的至少一些被打开时打开。通过掩模蚀刻硅层并沉积聚合物层。

10. 发明申请

US20080308526A1 Minimization of mask undercut on deep silicon etch 有权
标题翻译：在深硅蚀刻上最小化掩模底切
公开(公告)号：US20080308526A1
公开(公告)日：2008-12-18
申请号：US11820334
申请日：2007-06-18
申请人： Tamarak Pandhumsoporn , Patrick Chung , Jackie Seto , S.M. Reza Sadjadi
发明人： Tamarak Pandhumsoporn , Patrick Chung , Jackie Seto , S.M. Reza Sadjadi
IPC分类号： H01L21/3065 , B44C1/22
CPC分类号： H01L21/3086 , H01L21/31138
摘要： A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C4F8, forming a plasma from the deposition gas, depositing a polymer from the plasma for at least 20 seconds, and stopping the depositing the polymer after the at least 20 seconds. The deposited polymer layer is opened by flowing an opening gas, forming a plasma from the opening gas which selectively removes the deposited polymer on bottoms of the plurality of mask openings with respect to deposited polymer on sides of the plurality of mask openings, and stopping the opening when at least some of the plurality of mask features are opened. The silicon layer is etched through the mask and deposited polymer layer.
摘要翻译：提供了一种在硅层中形成特征的方法。在硅层上形成有多个掩模开口的掩模。通过使包含C4F8的无氢沉积气体从沉积气体形成等离子体，从等离子体沉积聚合物至少20秒，并在至少20秒后停止沉积聚合物，沉积聚合物层。沉积的聚合物层通过流动开口气体而打开，从开口气体形成等离子体，其在多个掩模开口的侧面上相对于沉积的聚合物选择性地去除多个掩模开口的底部上沉积的聚合物，并且停止当多个掩模特征中的至少一些被打开时打开。通过掩模蚀刻硅层并沉积聚合物层。

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