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1. 发明授权

US09680093B2 Nonvolatile memory element, nonvolatile memory device, nonvolatile memory element manufacturing method, and nonvolatile memory device manufacturing method 有权
公开(公告)号：US09680093B2
公开(公告)日：2017-06-13
申请号：US14343441
申请日：2012-09-10
申请人： Shinichi Yoneda , Takumi Mikawa , Satoru Ito , Yukio Hayakawa , Atsushi Himeno
发明人： Shinichi Yoneda , Takumi Mikawa , Satoru Ito , Yukio Hayakawa , Atsushi Himeno
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/124 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/1625 , H01L45/1675
摘要： A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide.

2. 发明申请

US20140197368A1 NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY ELEMENT MANUFACTURING METHOD, AND NONVOLATILE MEMORY DEVICE MANUFACTURING METHOD 有权
标题翻译：非易失性存储器元件，非易失性存储器件，非易失性存储元件制造方法和非易失性存储器件制造方法
公开(公告)号：US20140197368A1
公开(公告)日：2014-07-17
申请号：US14343441
申请日：2012-09-10
申请人： Shinichi Yoneda , Takumi Mikawa , Satoru Ito , Yukio Hayakawa , Atsushi Himeno
发明人： Shinichi Yoneda , Takumi Mikawa , Satoru Ito , Yukio Hayakawa , Atsushi Himeno
IPC分类号： H01L45/00
CPC分类号： H01L45/124 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/1625 , H01L45/1675
摘要： A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide.
摘要翻译：一种非易失性存储元件，包括：第一电极; 第二电极; 在第一电极和第二电极之间的可变电阻层，并且包括作为堆叠层的连接到第一电极的第一可变电阻层和连接到第二电极的第二可变电阻层; 以及具有阻氧性并覆盖可变电阻层的侧面的侧壁保护层。第一可变电阻层包括形成在第一金属氧化物周围的第一金属氧化物和第三金属氧化物，其氧缺陷低于第一金属氧化物，第二可变电阻层包括具有氧缺乏的第二金属氧化物低于第一金属氧化物。

3. 发明授权

US09214628B2 Nonvolatile memory element, nonvolatile memory device, and manufacturing method for the same 有权
标题翻译：非易失性存储元件，非易失性存储器件及其制造方法
公开(公告)号：US09214628B2
公开(公告)日：2015-12-15
申请号：US13810245
申请日：2011-11-30
申请人： Atsushi Himeno , Haruyuki Sorada , Yukio Hayakawa , Takumi Mikawa
发明人： Atsushi Himeno , Haruyuki Sorada , Yukio Hayakawa , Takumi Mikawa
IPC分类号： H01L45/00 , H01L27/10 , H01L27/24 , H01L27/105
CPC分类号： H01L45/1253 , H01L27/101 , H01L27/1052 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1625 , H01L45/1675
摘要： A nonvolatile memory element according to the present invention includes a first metal line; a plug formed on the first metal line and connected to the first metal line; a stacked structure including a first electrode, a second electrode, and a variable resistance layer, the stacked structure being formed on a plug which is connected to the first electrode; a second metal line formed on the stacked structure and directly connected to the second electrode; and a side wall protective layer which covers the side wall of the stacked structure and has an insulating property and an oxygen barrier property, wherein part of a lower surface of the second metal line is located under an upper surface of the stacked structure.
摘要翻译：根据本发明的非易失性存储元件包括第一金属线; 形成在所述第一金属线上并连接到所述第一金属线的插头; 包括第一电极，第二电极和可变电阻层的堆叠结构，所述堆叠结构形成在连接到所述第一电极的插头上; 形成在所述堆叠结构上并直接连接到所述第二电极的第二金属线; 以及侧壁保护层，其覆盖层叠结构的侧壁，并且具有绝缘性和氧阻隔性，其中第二金属线的下表面的一部分位于堆叠结构的上表面的下方。

4. 发明申请

US20130112935A1 NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY DEVICE, AND MANUFACTURING METHOD FOR THE SAME 有权
标题翻译：非易失性存储元件，非易失性存储器件及其制造方法
公开(公告)号：US20130112935A1
公开(公告)日：2013-05-09
申请号：US13810245
申请日：2011-11-30
申请人： Atsushi Himeno , Haruyuki Sorada , Yukio Hayakawa , Takumi Mikawa
发明人： Atsushi Himeno , Haruyuki Sorada , Yukio Hayakawa , Takumi Mikawa
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/101 , H01L27/1052 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1625 , H01L45/1675
摘要： A nonvolatile memory element according to the present invention includes a first metal line; a plug formed on the first metal line and connected to the first metal line; a stacked structure including a first electrode, a second electrode, and a variable resistance layer, the stacked structure being formed on a plug which is connected to the first electrode; a second metal line formed on the stacked structure and directly connected to the second electrode; and a side wall protective layer which covers the side wall of the stacked structure and has an insulating property and an oxygen barrier property, wherein part of a lower surface of the second metal line is located under an upper surface of the stacked structure.
摘要翻译：根据本发明的非易失性存储元件包括第一金属线; 形成在所述第一金属线上并连接到所述第一金属线的插头; 包括第一电极，第二电极和可变电阻层的堆叠结构，所述堆叠结构形成在连接到所述第一电极的插头上; 形成在所述堆叠结构上并直接连接到所述第二电极的第二金属线; 以及侧壁保护层，其覆盖层叠结构的侧壁，并且具有绝缘性和氧阻隔性，其中第二金属线的下表面的一部分位于堆叠结构的上表面的下方。

5. 发明申请

US20130149815A1 NONVOLATILE MEMORY ELEMENT MANUFACTURING METHOD AND NONVOLATILE MEMORY ELEMENT 审中-公开
标题翻译：非易失性存储元件制造方法和非易失性存储元件
公开(公告)号：US20130149815A1
公开(公告)日：2013-06-13
申请号：US13810465
申请日：2012-09-10
申请人： Hideaki Murase , Takumi Mikawa , Yoshio Kawashima , Atsushi Himeno
发明人： Hideaki Murase , Takumi Mikawa , Yoshio Kawashima , Atsushi Himeno
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A method of manufacturing a nonvolatile memory element includes: forming a first conductive film above a substrate; forming, above the first conductive film, a first metal oxide layer and a second metal oxide layer having different degrees of oxygen deficiency and a second conductive film; forming a second electrode by patterning the second conductive film; forming a variable resistance layer by patterning the first metal oxide layer and the second metal oxide layer; removing a side portion of the variable resistance layer in a surface parallel to a main surface of the substrate to a position that is further inward than an edge of the second electrode; and forming a first electrode by patterning the first conductive film after or during the removing.
摘要翻译：一种制造非易失性存储元件的方法包括：在衬底上形成第一导电膜; 在第一导电膜上方形成具有不同程度的氧缺陷的第一金属氧化物层和第二金属氧化物层和第二导电膜; 通过图案化第二导电膜形成第二电极; 通过图案化第一金属氧化物层和第二金属氧化物层来形成可变电阻层; 将平行于所述基板的主表面的表面中的所述可变电阻层的侧部移除到比所述第二电极的边缘更靠内侧的位置; 以及通过在去除之后或期间对第一导电膜进行图案化而形成第一电极。

6. 发明授权

US08394669B2 Resistance variable element and resistance variable memory device 有权
标题翻译：电阻可变元件和电阻变量存储器件
公开(公告)号：US08394669B2
公开(公告)日：2013-03-12
申请号：US13128575
申请日：2010-07-12
申请人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
IPC分类号： H01L21/02 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1666 , H01L45/1675
摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
摘要翻译：在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2），在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触彼此仅在更靠近基板的通孔的开口（20）中。

7. 发明授权

US08445883B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08445883B2
公开(公告)日：2013-05-21
申请号：US13126975
申请日：2009-07-16
申请人： Atsushi Himeno , Takumi Mikawa , Yoshio Kawashima
发明人： Atsushi Himeno , Takumi Mikawa , Yoshio Kawashima
IPC分类号： H01L29/02
CPC分类号： H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1683
摘要： A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided. A nonvolatile semiconductor memory device comprises a substrate; a plurality of stripe-shaped lower copper wires (70) formed on the substrate; an interlayer insulating layer (76) formed on the substrate provided with the lower copper wires (70), a plurality of contact holes penetrating interlayer insulating layer (76) to surfaces of the lower copper wires (70), respectively; electrode seed layers (77) and precious metal electrode layers (78) formed only at bottoms of the contact holes, respectively; resistance variable layers (73) filled into the contact holes such that the resistance variable layers are connected to the precious metal electrode layers (73), respectively; a plurality of stripe-shaped upper copper wires (74) connected to the resistance variable layers (73), respectively, and cross the lower copper wires (70), respectively, and the electrode seed layers (77) and the precious metal electrode layers (78) are formed by selective growth plating.
摘要翻译：提供一种非易失性半导体存储器件及其制造方法，该非易失性半导体存储器件分别在字线和位线的交叉点处的接触孔内部形成存储单元的交叉点结构中的小型化和较大容量。非易失性半导体存储器件包括衬底; 形成在所述基板上的多个条状下部铜线（70）形成在设置有下铜线（70）的基板上的层间绝缘层（76），分别向下铜线（70）的表面贯穿层间绝缘层（76）的多个接触孔; 电极种子层（77）和仅在接触孔的底部形成的贵金属电极层（78）; 电阻变化层（73）填充到接触孔中，使得电阻变化层分别连接到贵金属电极层（73）; 分别连接到电阻变化层（73）的多个条状上部铜线（74），分别与下部铜线（70）交叉，电极种子层（77）和贵金属电极层（78）通过选择性生长电镀形成。

8. 发明申请

US20120104350A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：可变电阻非易失性存储器件及其制造方法
公开(公告)号：US20120104350A1
公开(公告)日：2012-05-03
申请号：US13379460
申请日：2011-04-26
申请人： Atsushi Himeno , Haruyuki Sorada , Takumi Mikawa
发明人： Atsushi Himeno , Haruyuki Sorada , Takumi Mikawa
IPC分类号： H01L27/26 , H01L47/00
CPC分类号： H01L27/2463 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/1633
摘要： A step of forming, on a substrate (11), lower layer copper lines (18) each being shaped into a strip, a step of forming electrode seed layers (21) each being shaped into a strip, on the surfaces of the respective lower layer copper lines (18) using electroless plating, a step of forming interlayer insulating layer (19) above the electrode seed layers (21) and the substrate (11), a step of forming, in the interlayer insulating layer (19), memory cell holes (20), penetrating through the interlayer insulating layer (19) and extending to the electrode seed layers (21), a step of forming noble metal electrode layers (29) on the surfaces of the electrode seed layers (21) exposed in the respective memory cell holes (20) using the electroless plating, a step of forming, in the respective memory cell holes (20), variable resistance layers (23) connected to the noble electrode layers (29), and a step of forming, above the interlayer insulating layer (19) and the variable resistance layers (23), upper layer copper lines (24) each being shaped into a strip, connected to a corresponding one of the variable resistance layers (23), and crossing the lower layer copper lines (18), are included.
摘要翻译：在基板（11）上形成各自被成形为条带的下层铜线（18）的步骤，在各自的下表面上形成各自成形为条带的电极种子层（21）的步骤使用无电镀的层间铜线（18），在电极种子层（21）和基板（11）的上方形成层间绝缘层（19）的工序，在层间绝缘层（19）穿过层间绝缘层（19）并延伸到电极种子层（21）的电池孔（20），在暴露于电极种子层（21）的表面上形成贵金属电极层（29）的步骤使用无电镀的各个存储单元孔（20），在各个存储单元孔（20），连接到贵金属电极层（29）的可变电阻层（23）上形成步骤，在层间绝缘层（19）和可变电阻层（23）之上，上层铜线（24）各自被成形为条，连接到相应的一个可变电阻层（23）并与下层铜线（18）交叉。

9. 发明申请

US20110220862A1 RESISTANCE VARIABLE ELEMENT AND RESISTANCE VARIABLE MEMORY DEVICE 有权
标题翻译：电阻可变元件和电阻可变存储器件
公开(公告)号：US20110220862A1
公开(公告)日：2011-09-15
申请号：US13128575
申请日：2010-07-12
申请人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1666 , H01L45/1675
摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
摘要翻译：在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2），在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触彼此仅在更靠近基板的通孔的开口（20）中。

10. 发明申请

US20110220861A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110220861A1
公开(公告)日：2011-09-15
申请号：US13126975
申请日：2009-07-16
申请人： Atsushi Himeno , Takumi Mikawa , Yoshio Kawashima
发明人： Atsushi Himeno , Takumi Mikawa , Yoshio Kawashima
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1683
摘要： A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided. A nonvolatile semiconductor memory device comprises a substrate; a plurality of stripe-shaped lower copper wires (70) formed on the substrate; an interlayer insulating layer (76) formed on the substrate provided with the lower copper wires (70), a plurality of contact holes penetrating interlayer insulating layer (76) to surfaces of the lower copper wires (70), respectively; electrode seed layers (77) and precious metal electrode layers (78) formed only at bottoms of the contact holes, respectively; resistance variable layers (73) filled into the contact holes such that the resistance variable layers are connected to the precious metal electrode layers (73), respectively; a plurality of stripe-shaped upper copper wires (74) connected to the resistance variable layers (73), respectively, and cross the lower copper wires (70), respectively, and the electrode seed layers (77) and the precious metal electrode layers (78) are formed by selective growth plating.
摘要翻译：提供一种非易失性半导体存储器件及其制造方法，该非易失性半导体存储器件分别在字线和位线的交叉点处的接触孔内部形成存储单元的交叉点结构中的小型化和较大容量。非易失性半导体存储器件包括衬底; 形成在所述基板上的多个条状下部铜线（70）形成在设置有下铜线（70）的基板上的层间绝缘层（76），分别向下铜线（70）的表面贯穿层间绝缘层（76）的多个接触孔; 电极种子层（77）和仅在接触孔的底部形成的贵金属电极层（78）; 电阻变化层（73）填充到接触孔中，使得电阻变化层分别连接到贵金属电极层（73）; 分别连接到电阻变化层（73）的多个条状上部铜线（74），并分别与下部铜线（70）交叉，电极种子层（77）和贵金属电极层（78）通过选择性生长电镀形成。

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