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1. 发明授权

US06395619B2 Process for fabricating a semiconductor device 有权
标题翻译：制造半导体器件的工艺
公开(公告)号：US06395619B2
公开(公告)日：2002-05-28
申请号：US09203330
申请日：1998-12-02
申请人： Takuji Tanigami , Kenji Hakozaki , Naoyuki Shinmura , Shinichi Sato , Masanori Yoshimi , Takayuki Taniguchi
发明人： Takuji Tanigami , Kenji Hakozaki , Naoyuki Shinmura , Shinichi Sato , Masanori Yoshimi , Takayuki Taniguchi
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： The present invention provides a process for fabricating semiconductor device comprising the steps of: forming an etching-stop layer on a semiconductor substrate; patterning the etching-stop layer so that the etching-stop layer remains in a region to be an active region and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the semiconductor substrate an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer above the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting semiconductor substrate for flattening after removing the resist pattern.
摘要翻译：本发明提供一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成蚀刻停止层; 图案化蚀刻停止层，使得蚀刻停止层保持在作为有源区的区域中，并从作为器件隔离区的区域去除，然后在该区域中形成作为器件隔离区的沟槽; 在半导体衬底上沉积厚度大于或等于沟槽深度的绝缘膜; 形成抗蚀剂图案，其具有在与宽度大于或等于预定值的器件隔离区相邻的有源区上方的蚀刻停止层上方的开口，然后使用抗蚀剂图案作为掩模蚀刻绝缘膜; 并且在除去抗蚀剂图案之后，对存在于所得半导体衬底上的绝缘膜进行抛光以使其变平。

2. 发明授权

US5708600A Method for writing multiple value into nonvolatile memory in an equal time 失效
标题翻译：在同一时间内将多个值写入非易失性存储器的方法
公开(公告)号：US5708600A
公开(公告)日：1998-01-13
申请号：US725661
申请日：1996-10-01
申请人： Kenji Hakozaki , Shinichi Sato , Takuji Tanigami
发明人： Kenji Hakozaki , Shinichi Sato , Takuji Tanigami
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02
CPC分类号： G11C11/5628 , G11C11/5621
摘要： There is provided a method for writing a multiple value into a nonvolatile memory capable of writing multiple value data into a floating gate type memory cell in an equal time even when the data are varied. With a specified voltage applied to a control gate of a memory cell, a drain voltage which is varied according to each of data values "11", "10" and "01" to a drain so that a write time required for setting a varied threshold voltage is equalized. By moving electrons between a floating gate and a drain through a gate insulating film, the threshold voltage of the memory cell is set.
摘要翻译：提供了一种用于将多值写入非易失性存储器的方法，该非易失性存储器能够在相等的时间内将多值数据写入浮置型存储单元，即使数据变化。利用施加到存储单元的控制栅极的指定电压，将漏极电压根据数据值“11”，“10”和“01”中的每一个变化到漏极，使得设置变化的所需的写入时间阈值电压相等。通过栅极绝缘膜在浮置栅极和漏极之间移动电子，设定存储单元的阈值电压。

3. 发明授权

US5599727A Method for producing a floating gate memory device including implanting ions through an oxidized portion of the silicon film from which the floating gate is formed 失效
标题翻译：一种用于制造浮栅存储器件的方法，包括通过形成浮栅的硅膜的氧化部分注入离子
公开(公告)号：US5599727A
公开(公告)日：1997-02-04
申请号：US456867
申请日：1995-06-01
申请人： Kenji Hakozaki , Shin-ichi Sato
发明人： Kenji Hakozaki , Shin-ichi Sato
IPC分类号： H01L21/8247
CPC分类号： H01L27/11517
摘要： According to the present invention, a method for producing a nonvolatile semiconductor memory device is provided. The method includes the steps of: forming stripe-shaped silicon portions including a plurality of first portions to be used as a plurality of floating gates and a plurality of second portions interposed between two adjacent portions of the plurality of first portions by patterning a silicon film; forming a conductive film so as to cover an insulating film; forming a control gate so as to cover the plurality of first portions of the stripe-shaped silicon portions by patterning the conductive film; converting the plurality of second portions of the stripe-shaped silicon portions into a silicon oxide film, and forming the plurality of floating gates from the plurality of first portions by thermally oxidizing the plurality of second portions; and implanting impurity ions through the silicon oxide film into the active region on the semiconductor substrate by using the control gate as a mask, thereby forming a source region and a drain region in the active region.
摘要翻译：根据本发明，提供一种用于制造非易失性半导体存储器件的方法。该方法包括以下步骤：通过图案化硅膜来形成包括多个用作多个浮动栅极的第一部分和多个第二部分的条形硅部分，该多个第二部分插入在多个第一部分的两个相邻部分之间 ; 形成导电膜以覆盖绝缘膜; 通过图案化所述导电膜，形成控制栅极以覆盖所述条形硅部分的所述多个第一部分; 将条形硅部分的多个第二部分转换成氧化硅膜，并通过热氧化多个第二部分从多个第一部分形成多个浮动栅极; 以及通过使用所述控制栅极作为掩模将杂质离子注入到所述半导体衬底上的有源区中，从而在所述有源区中形成源区和漏区。

4. 发明授权

US6091637A Method for writing data into non-volatile semiconductor memory cell 有权
标题翻译：将数据写入非易失性半导体存储单元的方法
公开(公告)号：US6091637A
公开(公告)日：2000-07-18
申请号：US144317
申请日：1998-08-31
申请人： Kenji Hakozaki
发明人： Kenji Hakozaki
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C16/34 , G11C7/02
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： A method including: a first writing step for writing data by injecting electrons into the floating gate; a first verifying step for verifying whether the threshold voltage is higher than the first reference level after performing the first writing operation; a step of repeating the first writing step and the first verifying step until the threshold voltage becomes higher than the first reference level, if the threshold voltage is lower than the first reference level; a second verifying step for verifying whether the threshold voltage is higher than a second reference level which is set to be higher than the first reference level, if the threshold voltage is higher than the first reference level; a step of ending the writing operation if the threshold voltage is lower than the second reference level; and a second writing step for writing data by discharging electrons from the floating gate until the threshold voltage becomes higher than the first reference level and lower than the second reference level, if the threshold voltage is higher than the second reference level.
摘要翻译：一种方法，包括：第一写入步骤，用于通过将电子注入浮动栅极来写入数据; 第一验证步骤，用于在执行第一写入操作之后验证阈值电压是否高于第一参考电平; 如果阈值电压低于第一参考电平，则重复第一写入步骤和第一验证步骤直到阈值电压变得高于第一参考电平的步骤; 第二验证步骤，用于如果阈值电压高于第一参考电平，则验证阈值电压是否高于被设置为高于第一参考电平的第二参考电平; 如果阈值电压低于第二参考电平，则结束写入操作的步骤; 以及第二写入步骤，如果所述阈值电压高于所述第二参考电平，则通过从所述浮置栅极释放电子直到所述阈值电压变得高于所述第一参考电平并且低于所述第二参考电平来写入数据。

5. 发明授权

US07053440B2 Non-volatile semiconductor memory device and manufacturing method of the same 失效
标题翻译：非易失性半导体存储器件及其制造方法相同
公开(公告)号：US07053440B2
公开(公告)日：2006-05-30
申请号：US10778204
申请日：2004-02-17
申请人： Kenji Hakozaki , Kenichi Tanaka
发明人： Kenji Hakozaki , Kenichi Tanaka
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A non-volatile semiconductor memory device comprising: a first conductive type well formed within a semiconductor substrate; and a memory cell having a gate insulating film, a floating gate, an insulating film, a control gate and a pair of source/drain region, the gate insulating film, the floating gate, the insulating film, the control gate being layered in this order above the first conductive type well, the pair of source/drain regions being made up of second conductive type diffusion layers and formed within the first conductive type well, wherein the source region is electrically connected to the first conductive type well.
摘要翻译：一种非易失性半导体存储器件，包括：形成在半导体衬底内的第一导电类型阱; 以及具有栅极绝缘膜，浮动栅极，绝缘膜，控制栅极和一对源极/漏极区域的存储单元，栅极绝缘膜，浮动栅极，绝缘膜，控制栅极层叠在该所述一对源极/漏极区由第二导电型扩散层构成并形成在第一导电型阱内，其中源区电连接到第一导电型阱。

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