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1. 发明授权

US5276573A Slider unit controllably actuated at a surface of a moving information recording medium 失效
标题翻译：滑块单元可控制地在移动信息记录介质的表面上致动
公开(公告)号：US5276573A
公开(公告)日：1994-01-04
申请号：US801352
申请日：1991-12-02
申请人： Takeshi Harada , Masatoshi Kanamaru , Atsushi Hosogane , Akiomi Kohno , Kenji Mori
发明人： Takeshi Harada , Masatoshi Kanamaru , Atsushi Hosogane , Akiomi Kohno , Kenji Mori
IPC分类号： G11B5/60 , G11B21/21
CPC分类号： G11B5/6005 , G11B21/21 , G11B5/483
摘要： A slider unit having a reading or reproducing head, with the head being adapted to float over a surface of an information recording disc. The slider unit includes a slider body having a flying height sensor with float surfaces on an underside thereof to generate a lifting force. A piezoelectrically or electrostatically controlled valve layer may be positioned over a vent communicating between an upper surface of the slider, with the vent opening to a recess for generating a negative lift component at an underside of the slider unit. The slider body is made from a ceramic base portion and includes a semiconductive insert portion of, for example, silicon or a photosensitive glass with an adjustment device being formed by utilization of microfabrication techniques such as deposition and etching.
摘要翻译：具有读取或再现头的滑块单元，其头部适于在信息记录盘的表面上浮动。滑块单元包括具有飞行高度传感器的滑块体，浮体表面在其下侧以产生提升力。压电或静电控制的阀层可以位于在滑块的上表面之间连通的通风口上，通气口通向凹槽，用于在滑块单元的下侧产生负提升部件。滑块体由陶瓷基部制成，并且包括例如硅或感光玻璃的半导体插入部分，其中调整装置通过利用诸如沉积和蚀刻的微细加工技术形成。

2. 发明授权

US5163209A Method of manufacturing a stack-type piezoelectric element 失效
标题翻译：堆叠型压电元件的制造方法
公开(公告)号：US5163209A
公开(公告)日：1992-11-17
申请号：US510875
申请日：1990-04-18
申请人： Takeshi Harada , Masatoshi Kanamaru , Akiomi Kohno , Shigeru Jomura
发明人： Takeshi Harada , Masatoshi Kanamaru , Akiomi Kohno , Shigeru Jomura
IPC分类号： H01L41/047 , H01L41/083 , H01L41/297
CPC分类号： H01L41/297 , H01L41/0477 , H01L41/083 , Y10T29/42
摘要： In an overall stacked piezoelectric element, the material for the electrode was selected from aluminum, nickel and copper each alone or alloys based on aluminum, nickel or copper, and further the parts of the electrode which contact with molding resin on the side face of the stacked body and the parts which have to be insulated from the lead-out terminals were subjected to an oxidation or nitriding treatment. As the result, an improved element was obtained which is of a high reliability, suited to low voltage operation and suffers no short-circuit of the electrode even when water permeates to the side face of the stacked body during operation in humid atmosphere.

3. 发明授权

US07119362B2 Method of manufacturing semiconductor apparatus 有权
公开(公告)号：US07119362B2
公开(公告)日：2006-10-10
申请号：US10326663
申请日：2002-12-23
申请人： Ryuji Kono , Makoto Kitano , Hideo Miura , Hiroyuki Ota , Yoshishige Endo , Takeshi Harada , Masatoshi Kanamaru , Teruhisa Akashi , Atsushi Hosogane , Akihiko Ariga , Naoto Ban
发明人： Ryuji Kono , Makoto Kitano , Hideo Miura , Hiroyuki Ota , Yoshishige Endo , Takeshi Harada , Masatoshi Kanamaru , Teruhisa Akashi , Atsushi Hosogane , Akihiko Ariga , Naoto Ban
IPC分类号： H01L23/58
CPC分类号： G01R1/07314 , G01R1/06744 , G01R3/00 , G01R31/2863
摘要： In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.

4. 发明授权

US06511857B1 Process for manufacturing semiconductor device 有权
标题翻译：半导体器件制造工艺
公开(公告)号：US06511857B1
公开(公告)日：2003-01-28
申请号：US09646511
申请日：2001-01-12
申请人： Ryuji Kono , Makoto Kitano , Hideo Miura , Hiroyuki Ota , Yoshishige Endo , Takeshi Harada , Masatoshi Kanamaru , Teruhisa Akashi , Atsushi Hosogane , Akihiko Ariga , Naoto Ban
发明人： Ryuji Kono , Makoto Kitano , Hideo Miura , Hiroyuki Ota , Yoshishige Endo , Takeshi Harada , Masatoshi Kanamaru , Teruhisa Akashi , Atsushi Hosogane , Akihiko Ariga , Naoto Ban
IPC分类号： H01L2100
CPC分类号： G01R1/07314 , G01R1/06744 , G01R3/00 , G01R31/2863
摘要： In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.
摘要翻译：在与半导体装置制造工序相对应的电气特性测试过程中，为了一体地测试待测试体的电极焊盘的大面积面积，通过按压所提供的测试结构来进行电特性测试具有电数独立的突起，其数量等于要测试的被测体的待测试区域上待测试的导体部分的数量。

5. 发明授权

US06507204B1 Semiconductor testing equipment with probe formed on a cantilever of a substrate 失效
标题翻译：具有探针的半导体测试设备形成在基板的悬臂上
公开(公告)号：US06507204B1
公开(公告)日：2003-01-14
申请号：US09522477
申请日：2000-03-09
申请人： Masatoshi Kanamaru , Yoshishige Endo , Atsushi Hosogane , Tatsuya Nagata , Ryuji Kohno , Hideyuki Aoki , Akihiko Ariga
发明人： Masatoshi Kanamaru , Yoshishige Endo , Atsushi Hosogane , Tatsuya Nagata , Ryuji Kohno , Hideyuki Aoki , Akihiko Ariga
IPC分类号： G01R3102
CPC分类号： G01R1/06733 , G01R1/06727 , G01R1/06738 , G01R1/06761 , G01R1/06772 , G01R1/07342 , G01R3/00
摘要： The conventional semiconductor element testing equipment is arranged to position each probe accurately and need a burdensome operation for fixing, and includes only a limited number of electrode pads and chips to be tested at a batch. An equipment for testing a semiconductor element is arranged to keep each of electrode pads formed on a semiconductor element to be tested in direct contact with each of probes formed on a first substrate composed of silicon, one of electric connecting substrates disposed in the equipment. On the first substrate, each probe is formed on a cantilever and a wire is routed from a tip of each probe along a tip of the cantilever to the electrode pad formed on an opposite surface to the probe forming surface through an insulating layer.
摘要翻译：常规的半导体元件测试设备被布置成准确地定位每个探针，并且需要用于固定的繁重的操作，并且仅包括有限数量的待批测试的电极焊盘和芯片。布置了用于测试半导体元件的设备，以使每个形成在要测试的半导体元件上的电极焊盘与形成在由设置在设备中的电连接基板之一的硅构成的第一基板上形成的每个探针直接接触。在第一基板上，每个探针形成在悬臂上，并且从每个探针的尖端沿着悬臂的尖端布线到通过绝缘层与探针形成表面相对的表面上形成的电极焊盘。

6. 发明授权

US06479305B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US06479305B2
公开(公告)日：2002-11-12
申请号：US09396732
申请日：1999-09-15
申请人： Ryuji Kono , Akihiko Ariga , Hideyuki Aoki , Hiroyuki Ohta , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Shinji Tanaka , Naoto Ban , Hideo Miura
发明人： Ryuji Kono , Akihiko Ariga , Hideyuki Aoki , Hiroyuki Ohta , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Shinji Tanaka , Naoto Ban , Hideo Miura
IPC分类号： H01L2166
CPC分类号： H01L21/6836 , H01L22/20 , H01L2221/68327 , H01L2924/0002 , H01L2924/014 , H01L2924/00
摘要： Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.
摘要翻译：半导体器件芯片制造和检查方法被公开，其中将半导体晶片切割成单独的LSI芯片。 LSI芯片重新排列并集成为预定数量。切割的LSI芯片集成在具有与LSI芯片的尺寸相当的尺寸的开口的夹具中。具有这种开口的夹具的至少一部分具有与LSI芯片大致相同的热膨胀系数。综合预定数量的芯片在随后的检查步骤中进行检查处理，从而提高效率并降低成本。

7. 发明授权

US06358762B1 Manufacture method for semiconductor inspection apparatus 失效
公开(公告)号：US06358762B1
公开(公告)日：2002-03-19
申请号：US09534302
申请日：2000-03-23
申请人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
发明人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
IPC分类号： G01R3126
CPC分类号： H01L22/32 , G01R1/06711 , G01R1/06738 , G01R1/07314 , G01R3/00 , H01L23/13 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes. A method of manufacturing the semiconductor inspection apparatus comprises the steps of forming a cover film on a surface of the silicon substrate and forming a plurality of probes of a polygonal cone shape or a circular cone shape through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a beam or a diaphragm for each probe through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a through hole corresponding to the probe through etching after patterning by photolithography, and after the cover film is removed, forming an insulating film on the surface of the silicon substrate, forming a metal film on a surface of the insulating film, and forming a wiring lead through etching after patterning by photolithography.

8. 发明授权

US06864568B2 Packaging device for holding a plurality of semiconductor devices to be inspected 失效
标题翻译：用于保持待检查的多个半导体器件的封装装置
公开(公告)号：US06864568B2
公开(公告)日：2005-03-08
申请号：US10252546
申请日：2002-09-24
申请人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
发明人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
IPC分类号： G01R31/26 , G01R1/04 , G01R1/073 , H01L21/66 , H01L23/02
CPC分类号： G01R1/0483 , H01L2924/0002 , H01L2924/00
摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.
摘要翻译：一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件并且延伸到包装装置的外部，使得探针连接到每个导电构件。

9. 发明授权

US06465264B1 Method for producing semiconductor device and apparatus usable therein 失效
标题翻译：用于制造半导体器件的方法和可用于其中的装置
公开(公告)号：US06465264B1
公开(公告)日：2002-10-15
申请号：US09654612
申请日：2000-09-01
申请人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
发明人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
IPC分类号： G01R3126
CPC分类号： G01R1/0483 , H01L2924/0002 , H01L2924/00
摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.
摘要翻译：一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件并且延伸到包装装置的外部，使得探针连接到每个导电构件。

10. 发明授权

US06714030B2 Semiconductor inspection apparatus 失效
标题翻译：半导体检测仪器
公开(公告)号：US06714030B2
公开(公告)日：2004-03-30
申请号：US10390412
申请日：2003-03-18
申请人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
发明人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
IPC分类号： G01R3102
CPC分类号： H01L22/32 , G01R1/06711 , G01R1/06738 , G01R1/07314 , G01R3/00 , H01L23/13 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes. A method of manufacturing the semiconductor inspection apparatus comprises the steps of forming a cover film on a surface of the silicon substrate and forming a plurality of probes of a polygonal cone shape or a circular cone shape through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a beam or a diaphragm for each probe through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a through hole corresponding to the probe through etching after patterning by photolithography, and after the cover film is removed, forming an insulating film on the surface of the silicon substrate, forming a metal film on a surface of the insulating film, and forming a wiring lead through etching after patterning by photolithography.
摘要翻译：可以一次共同地检查多个半导体器件的半导体检查装置，由于探针的精度等，以前难以进行。一种制造半导体检查装置的方法包括以下步骤：在硅衬底的表面上形成覆盖膜，并通过光刻图案化之后通过蚀刻形成多个锥形或圆锥形的多个探针，被去除，再次在硅衬底的表面上形成覆盖膜，并且通过光刻在图案化之后通过蚀刻形成用于每个探针的光束或隔膜，在除去覆盖膜之后，再次在硅表面上形成覆盖膜在通过光刻图案化之后通过蚀刻形成与探针对应的通孔，并且在除去覆盖膜之后，在硅衬底的表面上形成绝缘膜，在绝缘膜的表面上形成金属膜，以及通过光刻在图案化之后通过蚀刻形成布线引线。

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