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1. 发明授权

US06864568B2 Packaging device for holding a plurality of semiconductor devices to be inspected 失效
标题翻译：用于保持待检查的多个半导体器件的封装装置
公开(公告)号：US06864568B2
公开(公告)日：2005-03-08
申请号：US10252546
申请日：2002-09-24
申请人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
发明人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
IPC分类号： G01R31/26 , G01R1/04 , G01R1/073 , H01L21/66 , H01L23/02
CPC分类号： G01R1/0483 , H01L2924/0002 , H01L2924/00
摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.
摘要翻译：一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件并且延伸到包装装置的外部，使得探针连接到每个导电构件。

2. 发明授权

US06465264B1 Method for producing semiconductor device and apparatus usable therein 失效
标题翻译：用于制造半导体器件的方法和可用于其中的装置
公开(公告)号：US06465264B1
公开(公告)日：2002-10-15
申请号：US09654612
申请日：2000-09-01
申请人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
发明人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
IPC分类号： G01R3126
CPC分类号： G01R1/0483 , H01L2924/0002 , H01L2924/00
摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.
摘要翻译：一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件并且延伸到包装装置的外部，使得探针连接到每个导电构件。

3. 发明授权

US06614246B1 Probe structure 失效
标题翻译：探头结构
公开(公告)号：US06614246B1
公开(公告)日：2003-09-02
申请号：US09648452
申请日：2000-08-28
申请人： Ryuji Kohno , Tatsuya Nagata , Hiroya Shimizu , Toshio Miyatake , Hideo Miura
发明人： Ryuji Kohno , Tatsuya Nagata , Hiroya Shimizu , Toshio Miyatake , Hideo Miura
IPC分类号： G01R1073
CPC分类号： G01R1/07378
摘要： The invention provides a probe structure in which secondary electrodes of a main base material in which probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, whereby an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.
摘要翻译：本发明提供了一种探针结构，其中形成探针的主要基底材料的二次电极即使在大面积形成大量探针的情况下也可以与衬底侧的电极电连接，从而使大量的LSIs 可以在晶片测试过程中一次性地测试晶片，从而可以提高测试过程的效率。在探针结构中，由具有高刚性材料的插入体配置在其中形成有探针的主基材和基板侧之间，并且其中形成有探针的主基材的二次电极电连接到电极在基板侧经由插入件。

4. 发明授权

US06977514B2 Probe structure 失效
标题翻译：探头结构
公开(公告)号：US06977514B2
公开(公告)日：2005-12-20
申请号：US10625566
申请日：2003-07-24
申请人： Ryuji Kohno , Tatsuya Nagata , Hiroya Shimizu , Toshio Miyatake , Hideo Miura
发明人： Ryuji Kohno , Tatsuya Nagata , Hiroya Shimizu , Toshio Miyatake , Hideo Miura
IPC分类号： G01R1/073 , H01L21/66 , G01R31/28
CPC分类号： G01R1/07378
摘要： A probe structure is provided in which secondary electrodes of a main base material and probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, and an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.
摘要翻译：提供了一种探针结构，其中形成主基材和探针的二次电极可以在基板侧电连接到基板侧的电极，即使在大面积上形成大量的探针，使得晶片内的大量LSI 可以在晶片测试过程中一次性测试，并且可以提高测试过程的效率。在探针结构中，由具有高刚性材料的插入体配置在其中形成有探针的主基材和基板侧之间，并且其中形成有探针的主基材的二次电极电连接到电极在基板侧经由插入件。

5. 发明授权

US06828810B2 Semiconductor device testing apparatus and method for manufacturing the same 失效
标题翻译：半导体器件测试装置及其制造方法
公开(公告)号：US06828810B2
公开(公告)日：2004-12-07
申请号：US10207145
申请日：2002-07-30
申请人： Masatoshi Kanamaru , Yoshishige Endo , Takanori Aono , Ryuji Kohno , Hiroya Shimizu , Naoto Ban , Hideyuki Aoki
发明人： Masatoshi Kanamaru , Yoshishige Endo , Takanori Aono , Ryuji Kohno , Hiroya Shimizu , Naoto Ban , Hideyuki Aoki
IPC分类号： G01R3102
CPC分类号： G01R1/0466
摘要： A semiconductor device testing apparatus is realized, which allows contactors to be positioned throughout the wafer surface highly accurately for uniform contact, testing a large-sized wafer, and cost reduction. A plurality of divided contactor blocks is formed with a positioning groove. The groove is used to position the plurality of contactor blocks with a positioning frame. Because the contactor blocks are divided into plurals, it is less likely that a partial surface distortion affects other portions to impair surface flatness as compared with the case where a plurality of non-divided contactors is formed integrally, and the plurality of contactor blocks can be brought into contact with a wafer to be tested uniformly. Additionally, even though abnormality is generated in a part of the contactor blocks, only the part of the contactor blocks is replaced. Therefore, replacement costs can be reduced as compared with the case where a plurality of non-divided contactors is formed integrally.
摘要翻译：实现半导体器件测试装置，其允许接触器高精度地定位在整个晶片表面，用于均匀接触，测试大尺寸晶片以及降低成本。多个分开的接触器块形成有定位槽。凹槽用于定位具有定位框架的多个接触器块。由于接触器块被分成多个，与多个非分隔接触器形成为一体的情况相比，部分表面变形对其他部分的影响较小可能损害表面平坦度，并且多个接触器块可以与待测试的晶片均匀接触。此外，即使在接触器块的一部分中产生异常，仅更换接触器块的一部分。因此，与多个非分割接触器一体形成的情况相比，可以降低更换成本。

6. 发明申请

US20050032252A1 Testing apparatus for carrying out inspection of a semiconductor device 有权
标题翻译：用于对半导体器件进行检查的测试装置
公开(公告)号：US20050032252A1
公开(公告)日：2005-02-10
申请号：US10934046
申请日：2004-09-03
申请人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Hideyuki Aoki
发明人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Hideyuki Aoki
IPC分类号： G01R1/06 , G01R1/073 , G01R31/28 , H01L21/66 , G01R31/02 , G01R31/26
CPC分类号： G01R1/07314
摘要： A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer. The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.
摘要翻译：制造半导体器件的方法具有在晶片的主表面上形成半导体器件的形成工艺和用于测试形成在晶片上的半导体器件的缺陷的测试过程。测试过程包括使测试设备与半导体器件的测试电极接触的步骤。测试装置具有接触器，该接触器包括与待测半导体器件的测试电极接触的多个探针，以及与探针电连接并设置在与探针相对的表面上的二次电极; 电极通过导电装置与接触器电连通的基板。导电装置形成为在探针与测试电极接触的状态下施加到导电装置的应力大于在探针不与测试电极接触的状态下施加到导电装置的应力。

7. 发明授权

US06864695B2 Semiconductor device testing apparatus and semiconductor device manufacturing method using it 失效
标题翻译：半导体器件测试装置及其使用的半导体器件制造方法
公开(公告)号：US06864695B2
公开(公告)日：2005-03-08
申请号：US09925375
申请日：2001-08-10
申请人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Naoto Ban
发明人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Naoto Ban
IPC分类号： G01R1/073 , G01R3/00 , G01R31/28 , H01L21/66 , G01R31/02
CPC分类号： G01R3/00 , G01R1/07357
摘要： Since each wiring line is formed on one surface of the associated beam at a prescribed width over the entire length of the beam, the beam has the same sectional shape taken in the width direction at any point along an arbitrary longitudinal direction of the beam. As a result, the second moment of area, which is determined by the shapes of the beam and the wiring line, is uniform. This prevents a problem of the curvature of a beam varying locally when the beam is bent by a prescribed amount due to contact of the probe with a pad of a subject body. This, in turn, prevents local concentration of stress in the beams and thereby prevents breakage of the beam. Therefore, the probe structure can be miniaturized while the strength of the beams is kept at a required level, whereby a semiconductor device testing apparatus capable of accommodating many probes can be realized.
摘要翻译：由于每个布线在波束的整个长度上以规定的宽度形成在相关联的光束的一个表面上，所以光束在沿着光束的任意纵向方向的任何点处具有在宽度方向上取下的截面形状。结果，由光束和布线的形状确定的面积的第二时刻是均匀的。这防止了当由于探针与被检体的垫接触而使光束弯曲预定量时局部变化的光束曲率的问题。这反过来又防止梁中的局部应力集中，从而防止梁的断裂。因此，能够将光束的强度保持在所要求的水平，能够使探头结构小型化，能够实现容纳多个探针的半导体装置的测试装置。

8. 发明授权

US06955870B2 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06955870B2
公开(公告)日：2005-10-18
申请号：US10274422
申请日：2002-10-17
申请人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Hideyuki Aoki
发明人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Hideyuki Aoki
IPC分类号： G01R1/06 , G01R1/073 , G01R31/28 , H01L21/66 , G03C5/00
CPC分类号： G01R1/07314
摘要： A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer. The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.
摘要翻译：制造半导体器件的方法具有在晶片的主表面上形成半导体器件的形成工艺和用于测试形成在晶片上的半导体器件的缺陷的测试过程。测试过程包括使测试设备与半导体器件的测试电极接触的步骤。测试装置具有接触器，该接触器包括与待测半导体器件的测试电极接触的多个探针，以及与探针电连接并设置在与探针相对的表面上的二次电极; 电极通过导电装置与接触器电连通的基板。导电装置形成为在探针与测试电极接触的状态下施加到导电装置的应力大于在探针不与测试电极接触的状态下施加到导电装置的应力。

9. 发明授权

US06952110B2 Testing apparatus for carrying out inspection of a semiconductor device 有权
标题翻译：用于对半导体器件进行检查的测试装置
公开(公告)号：US06952110B2
公开(公告)日：2005-10-04
申请号：US10934046
申请日：2004-09-03
申请人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Hideyuki Aoki
发明人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Hideyuki Aoki
IPC分类号： G01R1/06 , G01R1/073 , G01R31/28 , H01L21/66 , G01R31/02
CPC分类号： G01R1/07314
摘要： A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device. The testing process includes bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including probes that come into contact with the test electrodes of the semiconductor device, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; and a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.
摘要翻译：制造半导体器件的方法具有在晶片的主表面上形成半导体器件的形成工艺和用于测试半导体器件的缺陷的测试过程。测试过程包括使测试设备与半导体器件的测试电极接触。测试装置具有接触器，其包括与半导体器件的测试电极接触的探针，以及与探针电连接并设置在与探针相对的表面上的次级电极; 以及电极通过导电装置与接触器电连通的基板。导电装置形成为在探针与测试电极接触的状态下施加到导电装置的应力大于在探针不与测试电极接触的状态下施加到导电装置的应力。

10. 发明授权

US06885208B2 Semiconductor device and test device for same 失效
标题翻译：半导体器件和测试装置相同
公开(公告)号：US06885208B2
公开(公告)日：2005-04-26
申请号：US10218596
申请日：2002-08-15
申请人： Toshio Miyatake , Tatsuya Nagata , Hiroya Shimizu , Ryuji Kohno , Hideyuki Aoki
发明人： Toshio Miyatake , Tatsuya Nagata , Hiroya Shimizu , Ryuji Kohno , Hideyuki Aoki
IPC分类号： G01R31/28 , G01R31/26 , G11C11/419 , G11C29/04 , H01L21/66 , H01L21/822 , H01L23/544 , H01L23/58 , H01L27/04
CPC分类号： H01L22/32 , G11C29/04 , G11C29/1201 , G11C2029/1206 , H01L22/34 , H01L2224/05554
摘要： A semiconductor device includes a quadrangular semiconductor substrate and a self test circuit formed on the semiconductor substrate. A plurality of pads are formed on the semiconductor substrate, which pads are coupled at least to the self test circuit. The semiconductor substrate includes four rectangular or square regions which each include a respective corner of the quadrangle, and at least two of the pads are respectively located on diagonally opposite ones of the regions from one another.
摘要翻译：半导体器件包括四边形半导体衬底和形成在半导体衬底上的自测电路。多个焊盘形成在半导体衬底上，这些焊盘至少耦合到自测电路。半导体衬底包括四个矩形或正方形区域，每个区域包括四边形的相应角部，并且至少两个衬垫分别位于彼此相对的一个区域上。

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