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1. 发明授权

US5793694A Semiconductor integrated circuit device having means for peak current reduction 失效
标题翻译：具有用于峰值电流降低的装置的半导体集成电路器件
公开(公告)号：US5793694A
公开(公告)日：1998-08-11
申请号：US767724
申请日：1996-12-17
申请人： Takesada Akiba , Hiroshi Otori , Masayuki Nakamura , Adin Hyslop
发明人： Takesada Akiba , Hiroshi Otori , Masayuki Nakamura , Adin Hyslop
IPC分类号： G11C11/406 , G11C11/407 , G11C11/409 , H01L27/10 , G11C8/00
CPC分类号： G11C11/406
摘要： The present invention is a method and apparatus for reducing the peak current for all the bit mats during a CAS-before-RAs refresh operation of a DRAM. To this end, a circuit is created to detect a CAS-before-RAS refresh operation. When a CBR refresh is detected, the amplifying of the bit mats are offset from each other, thereby staggering the time when each bit mat draws its peak current. In an alternative embodiment, when a CBR refresh is detected, the activation of the word lines are offset from each other, thereby staggering the time when each bit mat draws its peak current.
摘要翻译：本发明是一种用于在DRAM的在CAS之前的RA刷新操作期间减少所有位元件的峰值电流的方法和装置。为此，创建一个电路来检测CAS-before-RAS刷新操作。当检测到CBR刷新时，位层的放大彼此偏移，从而交错每个位元件绘制其峰值电流的时间。在替代实施例中，当检测到CBR刷新时，字线的激活彼此偏移，从而交错每个位元件绘制其峰值电流的时间。

2. 发明授权

US6028800A Sense amplifier driver having variable power-supply voltage 失效
标题翻译：具有可变电源电压的感应放大器驱动器
公开(公告)号：US6028800A
公开(公告)日：2000-02-22
申请号：US732777
申请日：1996-10-15
申请人： Takesada Akiba , Goro Kitsukawa , Hiroshi Otori , Masayuki Nakamura , Hideo Sunami , Adin Hyslop
发明人： Takesada Akiba , Goro Kitsukawa , Hiroshi Otori , Masayuki Nakamura , Hideo Sunami , Adin Hyslop
IPC分类号： G11C11/407 , G11C7/06 , G11C11/409 , H03K19/0175 , G11C16/04
CPC分类号： G11C7/065
摘要： An apparatus and method for a logic circuit that advantageously adapts to different operating voltages. In a preferred embodiment, a logic circuit of the present invention is implemented to drive a large capacitive load and includes a first driver, comprising a set of small, low-current drive transistors, a second driver, comprising a set of large, high-speed transistors, and an additional transistor connected between the two drivers. The additional transistor can be selectively enabled to speed up the operation of the logic circuit, and disabled to reduce the peak current of the logic circuit. The additional transistor is enabled by a voltage detection signal, which is active when the operating voltage of the chip is at a low level and inactive when the operating voltage of the chip is at a high level.
摘要翻译：一种用于逻辑电路的装置和方法，其有利地适应于不同的工作电压。在优选实施例中，实现本发明的逻辑电路以驱动大容性负载，并且包括第一驱动器，其包括一组小的，低电流的驱动晶体管，第二驱动器，包括一组大的，高速晶体管和连接在两个驱动器之间的附加晶体管。可以选择性地使能附加晶体管来加速逻辑电路的操作，并且不能减小逻辑电路的峰值电流。附加晶体管由电压检测信号使能，该电压检测信号当芯片的工作电压处于低电平时有效，并且当芯片的工作电压处于高电平时不起作用。

3. 发明申请

US20050243638A1 Memory device tester and method for testing reduced power states 有权
公开(公告)号：US20050243638A1
公开(公告)日：2005-11-03
申请号：US11173307
申请日：2005-07-01
申请人： Matthew Harrington , Van Huynh , Adin Hyslop
发明人： Matthew Harrington , Van Huynh , Adin Hyslop
IPC分类号： G11C7/10 , G11C8/00 , G11C29/02 , G11C29/50 , G11C29/56
CPC分类号： G11C29/024 , G11C7/1072 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/56 , G11C2029/5006 , G11C2207/2227
摘要： A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.

4. 发明授权

US06373127B1 Integrated capacitor on the back of a chip 有权
标题翻译：集成电容器在芯片背面
公开(公告)号：US06373127B1
公开(公告)日：2002-04-16
申请号：US09398884
申请日：1999-09-20
申请人： Daniel Baudouin , Adin Hyslop , Akitoshi Nishimura , Jeffrey Janzen , Mark Kressley
发明人： Daniel Baudouin , Adin Hyslop , Akitoshi Nishimura , Jeffrey Janzen , Mark Kressley
IPC分类号： H01L23495
CPC分类号： H01L24/32 , H01L23/4951 , H01L23/49589 , H01L24/06 , H01L24/48 , H01L24/73 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2224/85399 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01041 , H01L2924/01056 , H01L2924/01072 , H01L2924/01073 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/30107 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device is disclosed. The device includes an integrated circuit chip having integral de-coupling capacitors on the chip backside. The de-coupling capacitors includes a metal layer in intimate contact with the semiconductor substrate of the integrated circuit, a dielectric layer and a second metal layer. The second metal layer is segmented to form multiple capacitors, and each capacitor is interconnected to power supplies of the chip. Interconnection to different integrated circuit packages is provided. A method of making the semiconductor device is also disclosed.
摘要翻译：公开了一种半导体器件。该器件包括在芯片背面具有集成去耦电容器的集成电路芯片。去耦电容器包括与集成电路的半导体衬底紧密接触的金属层，电介质层和第二金属层。第二金属层被分段以形成多个电容器，并且每个电容器互连到芯片的电源。提供与不同集成电路封装的互连。还公开了制造半导体器件的方法。

5. 发明授权

US5321510A Serial video processor 失效
标题翻译：串行视频处理器
公开(公告)号：US5321510A
公开(公告)日：1994-06-14
申请号：US895146
申请日：1992-06-05
申请人： Jimmie D. Childers , Adin Hyslop
发明人： Jimmie D. Childers , Adin Hyslop
IPC分类号： G06T1/20 , H04N5/14
CPC分类号： G06T1/20 , H04N5/14
摘要： A system for real-time digital processing of a video signal using a large number of one-bit serial processor elements each of which operates on one pixel of a horizontal scan. The video signal is converted to digital by an A-to-D converter, and stored in a set of input registers, one register for each processor element. All of these input registers are loaded during a horizontal scan, as the input registers are addressed in sequence by a commutator. Each processor element includes a one-bit binary adder, a set of one-bit registers, and two one-bit wide data memories of a size to store data from several scans. The processor elements are all controlled in common by a sequencer, a state machine or a processor. The processed video data is transferred to an output register for each processor element, from which it is converted to a video signal by a D-to-A converter. A frame memory may be used to save a processed frame for use in convolving the next frame; the input of the frame memory is taken at the output registers, and the frame memory output is applied to the input registers.
摘要翻译：一种用于使用大量一位串行处理器元件对视频信号进行实时数字处理的系统，每个处理器单元在水平扫描的一个像素上进行操作。视频信号由A转D转换器转换为数字，并存储在一组输入寄存器中，每个处理器元件一个寄存器。所有这些输入寄存器在水平扫描期间被加载，因为输入寄存器依次由换向器寻址。每个处理器元件包括一位二进制加法器，一组一位寄存器和两个一位宽数据存储器，其大小用于存储来自多次扫描的数据。处理器元件都由定序器，状态机或处理器共同控制。经处理的视频数据被传送到每个处理器元件的输出寄存器，由D转换器转换成视频信号。可以使用帧存储器来保存用于卷积下一帧的处理帧; 帧存储器的输入在输出寄存器处获取，并且帧存储器输出被施加到输入寄存器。

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