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1. 发明授权

US6028800A Sense amplifier driver having variable power-supply voltage 失效
标题翻译：具有可变电源电压的感应放大器驱动器
公开(公告)号：US6028800A
公开(公告)日：2000-02-22
申请号：US732777
申请日：1996-10-15
申请人： Takesada Akiba , Goro Kitsukawa , Hiroshi Otori , Masayuki Nakamura , Hideo Sunami , Adin Hyslop
发明人： Takesada Akiba , Goro Kitsukawa , Hiroshi Otori , Masayuki Nakamura , Hideo Sunami , Adin Hyslop
IPC分类号： G11C11/407 , G11C7/06 , G11C11/409 , H03K19/0175 , G11C16/04
CPC分类号： G11C7/065
摘要： An apparatus and method for a logic circuit that advantageously adapts to different operating voltages. In a preferred embodiment, a logic circuit of the present invention is implemented to drive a large capacitive load and includes a first driver, comprising a set of small, low-current drive transistors, a second driver, comprising a set of large, high-speed transistors, and an additional transistor connected between the two drivers. The additional transistor can be selectively enabled to speed up the operation of the logic circuit, and disabled to reduce the peak current of the logic circuit. The additional transistor is enabled by a voltage detection signal, which is active when the operating voltage of the chip is at a low level and inactive when the operating voltage of the chip is at a high level.
摘要翻译：一种用于逻辑电路的装置和方法，其有利地适应于不同的工作电压。在优选实施例中，实现本发明的逻辑电路以驱动大容性负载，并且包括第一驱动器，其包括一组小的，低电流的驱动晶体管，第二驱动器，包括一组大的，高速晶体管和连接在两个驱动器之间的附加晶体管。可以选择性地使能附加晶体管来加速逻辑电路的操作，并且不能减小逻辑电路的峰值电流。附加晶体管由电压检测信号使能，该电压检测信号当芯片的工作电压处于低电平时有效，并且当芯片的工作电压处于高电平时不起作用。

2. 发明授权

US5793694A Semiconductor integrated circuit device having means for peak current reduction 失效
标题翻译：具有用于峰值电流降低的装置的半导体集成电路器件
公开(公告)号：US5793694A
公开(公告)日：1998-08-11
申请号：US767724
申请日：1996-12-17
申请人： Takesada Akiba , Hiroshi Otori , Masayuki Nakamura , Adin Hyslop
发明人： Takesada Akiba , Hiroshi Otori , Masayuki Nakamura , Adin Hyslop
IPC分类号： G11C11/406 , G11C11/407 , G11C11/409 , H01L27/10 , G11C8/00
CPC分类号： G11C11/406
摘要： The present invention is a method and apparatus for reducing the peak current for all the bit mats during a CAS-before-RAs refresh operation of a DRAM. To this end, a circuit is created to detect a CAS-before-RAS refresh operation. When a CBR refresh is detected, the amplifying of the bit mats are offset from each other, thereby staggering the time when each bit mat draws its peak current. In an alternative embodiment, when a CBR refresh is detected, the activation of the word lines are offset from each other, thereby staggering the time when each bit mat draws its peak current.
摘要翻译：本发明是一种用于在DRAM的在CAS之前的RA刷新操作期间减少所有位元件的峰值电流的方法和装置。为此，创建一个电路来检测CAS-before-RAS刷新操作。当检测到CBR刷新时，位层的放大彼此偏移，从而交错每个位元件绘制其峰值电流的时间。在替代实施例中，当检测到CBR刷新时，字线的激活彼此偏移，从而交错每个位元件绘制其峰值电流的时间。

3. 发明授权

US5844853A Memory regulator control method with flexibility for a wide change in supply voltage 失效
标题翻译：内存调节器控制方式具有灵活性，可大幅度改变电源电压
公开(公告)号：US5844853A
公开(公告)日：1998-12-01
申请号：US790610
申请日：1997-01-29
申请人： Goro Kitsukawa , Wah Kit Loh , Takesada Akiba , Masayuki Nakamura , Hiroshi Otori
发明人： Goro Kitsukawa , Wah Kit Loh , Takesada Akiba , Masayuki Nakamura , Hiroshi Otori
IPC分类号： G11C11/413 , G01R31/317 , G05F3/24 , G11C5/14 , G11C11/407 , G11C11/4074 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C7/10
CPC分类号： G01R31/31712 , G11C11/4074 , G11C5/147
摘要： A circuit and method for providing a plurality of voltage regulators whose outputs are constant for ranges of different external voltages are disclosed. The voltage regulators are made to be adaptable to two different ranges of external voltages through use of a master-slice technique. Furthermore, in a first voltage regulator, the supply current capability of the regulator is significantly increased under very low external voltage conditions. In a second voltage regulator, the voltage level on any node of the regulator does not exceed a voltage level that is too high, yet still sinks most of its current from the external power supply. A third voltage regulator is able to charge and discharge its output voltage so that it will maintain at a constant level. Finally, a fourth voltage regulator is optimized to reduce dielectric leakage.
摘要翻译：公开了一种用于提供多个稳压器的电路和方法，其输出对于不同外部电压的范围是恒定的。通过使用主切片技术，电压调节器可以适应两种不同的外部电压范围。此外，在第一电压调节器中，在非常低的外部电压条件下，调节器的电源电流能力显着增加。在第二个稳压器中，调节器任何节点上的电压电平都不会超过太高的电压电平，但仍然从外部电源中吸收大部分电流。第三电压调节器能够对其输出电压进行充电和放电，使其保持在恒定电平。最后，第四个电压调节器被优化以减少电介质泄漏。

4. 再颁专利

USRE38944E1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：USRE38944E1
公开(公告)日：2006-01-24
申请号：US09974962
申请日：2001-10-12
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and columns selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。子存储垫上面是：主字线和列选择信号线与正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

5. 发明授权

US5966341A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5966341A
公开(公告)日：1999-10-12
申请号：US982398
申请日：1997-12-02
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/10 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

6. 再颁专利

USRE42659E1 Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed 有权
标题翻译：大容量半导体存储器，具有改进的子放大器布局，以提高速度
公开(公告)号：USRE42659E1
公开(公告)日：2011-08-30
申请号：US11759316
申请日：2007-06-07
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及指定的子公共I / O线选择性地连接的主要公共I / O。

7. 发明授权

US5777927A Semiconductor memory 失效
公开(公告)号：US5777927A
公开(公告)日：1998-07-07
申请号：US779835
申请日：1997-01-07
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/10 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

8. 再颁专利

USRE41379E1 Large-Capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed 有权
标题翻译：大容量半导体存储器，具有改进的子放大器布局以提高操作速度
公开(公告)号：USRE41379E1
公开(公告)日：2010-06-15
申请号：US11759345
申请日：2007-06-07
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

9. 再颁专利

USRE40356E1 Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed 有权
标题翻译：大容量半导体存储器，具有改进的子放大器布局，以提高操作速度
公开(公告)号：USRE40356E1
公开(公告)日：2008-06-03
申请号：US11176881
申请日：2005-07-08
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

10. 发明授权

US5604697A Semiconductor 失效
标题翻译：半导体
公开(公告)号：US5604697A
公开(公告)日：1997-02-18
申请号：US574104
申请日：1995-12-20
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/10 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

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