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1. 发明授权

US06373127B1 Integrated capacitor on the back of a chip 有权
标题翻译：集成电容器在芯片背面
公开(公告)号：US06373127B1
公开(公告)日：2002-04-16
申请号：US09398884
申请日：1999-09-20
申请人： Daniel Baudouin , Adin Hyslop , Akitoshi Nishimura , Jeffrey Janzen , Mark Kressley
发明人： Daniel Baudouin , Adin Hyslop , Akitoshi Nishimura , Jeffrey Janzen , Mark Kressley
IPC分类号： H01L23495
CPC分类号： H01L24/32 , H01L23/4951 , H01L23/49589 , H01L24/06 , H01L24/48 , H01L24/73 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2224/85399 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01041 , H01L2924/01056 , H01L2924/01072 , H01L2924/01073 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/30107 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device is disclosed. The device includes an integrated circuit chip having integral de-coupling capacitors on the chip backside. The de-coupling capacitors includes a metal layer in intimate contact with the semiconductor substrate of the integrated circuit, a dielectric layer and a second metal layer. The second metal layer is segmented to form multiple capacitors, and each capacitor is interconnected to power supplies of the chip. Interconnection to different integrated circuit packages is provided. A method of making the semiconductor device is also disclosed.
摘要翻译：公开了一种半导体器件。该器件包括在芯片背面具有集成去耦电容器的集成电路芯片。去耦电容器包括与集成电路的半导体衬底紧密接触的金属层，电介质层和第二金属层。第二金属层被分段以形成多个电容器，并且每个电容器互连到芯片的电源。提供与不同集成电路封装的互连。还公开了制造半导体器件的方法。

2. 发明申请

US20070036006A1 System and method for mode register control of data bus operating mode and impedance 有权
标题翻译：数据总线工作模式和阻抗模式寄存器控制的系统和方法
公开(公告)号：US20070036006A1
公开(公告)日：2007-02-15
申请号：US11542702
申请日：2006-10-03
申请人： Jeffrey Janzen , Christopher Morzano
发明人： Jeffrey Janzen , Christopher Morzano
IPC分类号： G11C7/10
CPC分类号： G11C7/1045 , G11C7/1048 , G11C11/4096
摘要： A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.
摘要翻译： DRAM设备包括被编程为选择用于在设备中操作数据总线端子的两种模式之一的模式寄存器。定时电路产生与对应于所选模式的时钟信号同步的定时信号。定时信号与读数据信号组合，以产生相应的定时读数据信号。来自定时电路的这些定时数据信号和终止信号被施加到上拉和下拉电路，其驱动耦合到数据总线端子的相应上拉和下拉晶体管。如果选择了第一操作模式，则晶体管将数据总线端子驱动为第一或第二电压，并且如果选择了第二操作模式，则晶体管驱动到第三或第四电压。此外，上拉和下拉晶体管将数据总线端子偏置到对应于所选择的操作模式的相应电压。

3. 发明申请

US20060187740A1 System and method for mode register control of data bus operating mode and impedance 有权
标题翻译：数据总线工作模式和阻抗模式寄存器控制的系统和方法
公开(公告)号：US20060187740A1
公开(公告)日：2006-08-24
申请号：US11061035
申请日：2005-02-18
申请人： Jeffrey Janzen , Christopher Morzano
发明人： Jeffrey Janzen , Christopher Morzano
IPC分类号： G11C8/00
CPC分类号： G11C7/1045 , G11C7/1048 , G11C11/4096
摘要： A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.
摘要翻译： DRAM设备包括被编程为选择用于在设备中操作数据总线端子的两种模式之一的模式寄存器。定时电路产生与对应于所选模式的时钟信号同步的定时信号。定时信号与读数据信号组合，以产生相应的定时读数据信号。来自定时电路的这些定时数据信号和终止信号被施加到上拉和下拉电路，其驱动耦合到数据总线端子的相应上拉和下拉晶体管。如果选择了第一操作模式，则晶体管将数据总线端子驱动为第一或第二电压，并且如果选择了第二操作模式，则晶体管驱动到第三或第四电压。此外，上拉和下拉晶体管将数据总线端子偏置到对应于所选择的操作模式的相应电压。

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