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1. 发明授权

US06326218B1 Semiconductor integrated circuit and its manufacturing method 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06326218B1
公开(公告)日：2001-12-04
申请号：US09575442
申请日：2000-05-22
申请人： Takashi Yunogami , Kazuo Nojiri , Yuzuru Ohji , Sukeyoshi Tsunekawa , Masahiko Hiratani , Yuichi Matsui
发明人： Takashi Yunogami , Kazuo Nojiri , Yuzuru Ohji , Sukeyoshi Tsunekawa , Masahiko Hiratani , Yuichi Matsui
IPC分类号： H01G706
CPC分类号： H01L27/105 , H01L21/32139 , H01L27/11502 , H01L27/11507 , H01L27/11509 , H01L28/55 , H01L28/60
摘要： Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.
摘要翻译：描述了在图案化钌等上使用诸如铂或BST之类的薄膜作为硬掩模的集成电路的制造方法，从而可以在不去除硬掩模的情况下形成器件。另外，本发明的方法可以插入诸如铂的保护膜，以便在去除用于图案化硬掩模的抗蚀剂时，下面的钌膜等被损坏。

2. 发明授权

US06451665B1 Method of manufacturing a semiconductor integrated circuit 失效
标题翻译：制造半导体集成电路的方法
公开(公告)号：US06451665B1
公开(公告)日：2002-09-17
申请号：US09459343
申请日：1999-12-13
申请人： Takashi Yunogami , Kazuo Nojiri , Yuzuru Ohji , Sukeyoshi Tsunekawa , Masahiko Hiratani , Yuichi Matsui
发明人： Takashi Yunogami , Kazuo Nojiri , Yuzuru Ohji , Sukeyoshi Tsunekawa , Masahiko Hiratani , Yuichi Matsui
IPC分类号： H01L2120
CPC分类号： H01L27/105 , H01L21/32139 , H01L27/11502 , H01L27/11507 , H01L27/11509 , H01L28/55 , H01L28/60
摘要： Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.
摘要翻译：描述了在图案化钌等上使用诸如铂或BST之类的薄膜作为硬掩模的集成电路的制造方法，从而可以在不去除硬掩模的情况下形成器件。另外，本发明的方法可以插入诸如铂的保护膜，以便在去除用于图案化硬掩模的抗蚀剂时，下面的钌膜等被损坏。

3. 发明授权

US06720603B2 CAPACITOR STRUCTURE AND A SEMICONDUCTOR DEVICE WITH A FIRST METAL LAYER, A SECOND METAL SILICIDE LAYER FORMED OVER THE FIRST METAL LAYER AND A SECOND METAL LAYER FORMED OVER THE SECOND METAL SILICIDE LAYER 有权
标题翻译：电容器结构和具有第一金属层的第二金属层的第一金属层和在第二金属硅化物层上形成的第二金属层的第二金属层的半导体器件
公开(公告)号：US06720603B2
公开(公告)日：2004-04-13
申请号：US10321614
申请日：2002-12-18
申请人： Shinpei Iijima , Yuzuru Ohji , Masato Kunitomo , Masahiko Hiratani , Yuichi Matsui , Hiroyuki Ohta , Yukihiro Kumagai
发明人： Shinpei Iijima , Yuzuru Ohji , Masato Kunitomo , Masahiko Hiratani , Yuichi Matsui , Hiroyuki Ohta , Yukihiro Kumagai
IPC分类号： H01L27108
CPC分类号： H01L21/02183 , H01L21/02271 , H01L21/02337 , H01L21/02356 , H01L21/31637 , H01L27/10814 , H01L27/10855 , H01L28/60 , H01L28/91
摘要： A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.
摘要翻译：形成在DRAM的电容元件的下部电极上形成的电介质膜的氧气氛中的氧气的缺点是氧气渗透下部电极氧化阻挡层以形成高电阻和低介电常数的氧化物层。在形成在信息容纳电容元件C的下部电极下方的通孔中的插塞表面上形成Ru Ru硅化物层，并且在Ru硅化物层的表面上进一步形成Ru氮化硅层。在下电极上形成电介质膜的步骤中进行的氧气氛中进行高温热处理时，将Ru氮化硅层牺牲性氧化为Ru氮氧化硅，以防止Ru化硅化物层的氧化进行。

4. 发明授权

US06534375B2 METHOD OF FORMING A CAPACITOR IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING A METAL SILICON NITRIDE LAYER TO PROTECT AN UNDERLYING METAL SILICIDE LAYER FROM OXIDATION DURING SUBSEQUENT PROCESSING STEPS 有权
标题翻译：在半导体集成电路器件中形成电容器的方法使用金属硅化物层在后续处理步骤中从氧化物中保护金属硅酸盐层
公开(公告)号：US06534375B2
公开(公告)日：2003-03-18
申请号：US09923406
申请日：2001-08-08
申请人： Shinpei Iijima , Yuzuru Ohji , Masato Kunitomo , Masahiko Hiratani , Yuichi Matsui , Hiroyuki Ohta , Yukihiro Kumagai
发明人： Shinpei Iijima , Yuzuru Ohji , Masato Kunitomo , Masahiko Hiratani , Yuichi Matsui , Hiroyuki Ohta , Yukihiro Kumagai
IPC分类号： H01L21285
CPC分类号： H01L21/02183 , H01L21/02271 , H01L21/02337 , H01L21/02356 , H01L21/31637 , H01L27/10814 , H01L27/10855 , H01L28/60 , H01L28/91
摘要： A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.
摘要翻译：形成在DRAM的电容元件的下部电极上形成的电介质膜的氧气氛中的氧气的缺点是氧气渗透下部电极氧化阻挡层以形成高电阻和低介电常数的氧化物层。在形成在信息容纳电容元件C的下部电极下方的通孔中的插塞表面上形成Ru Ru硅化物层，并且在Ru硅化物层的表面上进一步形成Ru氮化硅层。在下电极上形成电介质膜的步骤中进行的氧气氛中进行高温热处理时，将Ru氮化硅层牺牲性氧化为Ru氮氧化硅，以防止Ru化硅化物层的氧化进行。

5. 发明授权

US06756262B1 Semiconductor integrated circuit device having spaced-apart electrodes and the method thereof 失效
标题翻译：具有间隔开的电极的半导体集成电路装置及其方法
公开(公告)号：US06756262B1
公开(公告)日：2004-06-29
申请号：US09708450
申请日：2000-11-09
申请人： Yoshitaka Nakamura , Isamu Asano , Satoru Yamada , Tsugio Takahashi , Yuzuru Ohji , Masayoshi Hirasawa , Takashi Yunogami , Tomonori Sekiguchi
发明人： Yoshitaka Nakamura , Isamu Asano , Satoru Yamada , Tsugio Takahashi , Yuzuru Ohji , Masayoshi Hirasawa , Takashi Yunogami , Tomonori Sekiguchi
IPC分类号： H01L218249
CPC分类号： H01L28/75 , H01L27/10814 , H01L27/10855 , H01L27/10894 , H01L28/55 , H01L28/65 , H01L28/90
摘要： Conduction reliability between a capacitor upper electrode and a plug connected to an upper layer wire is kept high to prevent connection defects and to reduce the resistance of the capacitor upper electrode. In a capacitor of a DRAM comprising a lower electrode 45 made of ruthenium, a capacitor insulating film 50 made of BST and an upper electrode 49, the upper electrode 49 has a laminate structure comprising a ruthenium film 47 formed on the side of the capacitor insulating film 50 and a tungsten film 48 formed over the former.
摘要翻译：电容器上部电极和连接到上层电线的插头之间的传导可靠性保持较高，以防止连接缺陷并降低电容器上部电极的电阻。在包括由钌制成的下电极45的电容器，由BST制成的电容器绝缘膜50和上电极49的情况下，上电极49具有包括形成在绝缘电容器侧的钌膜47的层叠结构膜50和形成在前者上的钨膜48。

6. 发明授权

US06426255B1 Process for making a semiconductor integrated circuit device having a dynamic random access memory 失效
标题翻译：制造具有动态随机存取存储器的半导体集成电路器件的工艺
公开(公告)号：US06426255B1
公开(公告)日：2002-07-30
申请号：US09549085
申请日：2000-04-13
申请人： Isamu Asano , Yoshitaka Nakamura , Yuzuru Ohji , Tatsuyuki Saito , Takashi Yunogami
发明人： Isamu Asano , Yoshitaka Nakamura , Yuzuru Ohji , Tatsuyuki Saito , Takashi Yunogami
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/2885 , H01L27/10814 , H01L27/10882 , H01L28/55 , H01L28/60
摘要： After formation of a groove in a silicon oxide film, a Pt film is formed inside of the groove by electroplating using a conductive underlying film, which has been formed in advance below the silicon oxide film, as a cathode electrode. The silicon oxide film is then removed by etching, followed by dry etching of the conductive underlying film with the Pt film as a mask, whereby a lower electrode of a capacitor is formed from the Pt film and the conductive underlying film which has remained below the Pt film.
摘要翻译：在氧化硅膜中形成沟槽之后，通过使用在氧化硅膜之前预先形成的导电性底膜进行电镀而在沟槽内部形成Pt膜作为阴极电极。然后通过蚀刻去除氧化硅膜，然后用Pt膜作为掩模对导电性底膜进行干蚀刻，由此由Pt膜和导电性底层膜形成电容器的下电极，该电极保持在低于 Pt膜。

7. 发明授权

US06255151B1 Semiconductor integrated circuit device and method of manufacturing same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06255151B1
公开(公告)日：2001-07-03
申请号：US09209013
申请日：1998-12-11
申请人： Takuya Fukuda , Yuzuru Ohji , Nobuyoshi Kobayashi
发明人： Takuya Fukuda , Yuzuru Ohji , Nobuyoshi Kobayashi
IPC分类号： H01L21336
CPC分类号： H01L27/10894 , H01L21/31053 , H01L23/53228 , H01L27/10814 , H01L27/10882 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.
摘要翻译：由电容器C引起的存储单元阵列区域和外围电路区域之间的阶梯状偏移通过具有基本上等于电容器C的高度的厚度的绝缘膜而减小。布线或互连槽限定在通过CMP方法将表面平坦化的绝缘膜的表面附近。此外，连接孔分别限定在互连槽的底面的下部。包含铜的第二层互连形成在互连槽内，并且在连接孔内形成包含铜的连接部分。第二层互连和第一层互连通过缩短长度的连接部彼此连接。第二层互连和连接部分通过使用CMP方法的镶嵌方法一体地形成。

8. 发明授权

US5188976A Manufacturing method of non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件的制造方法
公开(公告)号：US5188976A
公开(公告)日：1993-02-23
申请号：US727052
申请日：1991-07-09
申请人： Hitoshi Kume , Tetsuo Adachi , Yuzuru Ohji , Tokuo Kure , Masahiro Ushiyama , Hiroshi Kawakami
发明人： Hitoshi Kume , Tetsuo Adachi , Yuzuru Ohji , Tokuo Kure , Masahiro Ushiyama , Hiroshi Kawakami
IPC分类号： H01L21/8234 , H01L21/8247
CPC分类号： H01L27/11526 , H01L21/8234 , H01L27/11546
摘要： Before a high permittivity interlayer insulating film of a non-volatile memory having a two-level gate electrode structure, a surface of a substrate in a peripheral circuit MOS area is successively covered with a thermal oxide film and a polycrystalline silicon film. Before the interlayer insulating film is selectively removed on the peripheral circuit MOS area, the surface of the interlayer insulating film of the non-volatile memory is covered with a polycrystalline silicon film. When the interlayer insulating film in the peripheral circuit MOS area is removed, the polycrystalline silicon film as a lower layer in the peripheral circuit area serves as a buffer layer against contamination or damage due to the etching, and the conductive layer on the surface of the interlayer insulating film in the non-volatile memory portion also serves as a buffer layer against the contamination or damage due to the etching.
摘要翻译：在具有二电平栅电极结构的非易失性存储器的高介电常数层间绝缘膜之前，外围电路MOS区中的衬底的表面被热氧化膜和多晶硅膜依次覆盖。在外围电路MOS区域上选择性地除去层间绝缘膜之前，用多晶硅膜覆盖非易失性存储器的层间绝缘膜的表面。当外围电路MOS区域中的层间绝缘膜被去除时，外围电路区域中作为下层的多晶硅膜用作缓冲层，以防止由于蚀刻引起的污染或损坏，并且导电层非挥发性存储部分中的层间绝缘膜也用作抵抗由于蚀刻引起的污染或损伤的缓冲层。

9. 发明授权

US06881597B2 Method of manufacturing a semiconductor device to provide a plurality of test element groups (TEGs) in a scribe region 失效
标题翻译：制造半导体器件以在划线区域中提供多个测试元件组（TEG）的方法
公开(公告)号：US06881597B2
公开(公告)日：2005-04-19
申请号：US10051056
申请日：2002-01-22
申请人： Kyoichiro Asayama , Yasuhiro Mitsui , Fumiko Arakawa , Shiro Kamohara , Yuzuru Ohji
发明人： Kyoichiro Asayama , Yasuhiro Mitsui , Fumiko Arakawa , Shiro Kamohara , Yuzuru Ohji
IPC分类号： G01R31/28 , H01L21/28 , H01L21/3205 , H01L21/66 , H01L21/822 , H01L23/52 , H01L23/544 , H01L27/04 , H01L21/00
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed is a technique capable of improving a yield of a semiconductor device by measuring a plurality of TEGs arranged in a scribe region. A first electrode pad connected to each terminal of a TEG is formed as a rectangular, minute, isolated pattern having a side length of about 0.5 μm or shorter and constituted of an uppermost layer wiring on a semiconductor substrate, and therefore, a great number of TEGs can be laid in a first scribe region. The characteristic evaluation or the failure analysis is performed by contacting a nanoprobe having a tip radius of curvature of 0.05 μm to 0.8 μm to the first electrode pad.
摘要翻译：公开了一种能够通过测量布置在划线区域中的多个TEG来提高半导体器件的产量的技术。连接到TEG的每个端子的第一电极焊盘形成为具有约0.5μm或更短的侧边长度并由半导体衬底上的最上层布线构成的矩形，微小隔离图案，因此，大量 TEG可以放在第一个划痕区域。特征评估或故障分析是通过将具有0.05μm至0.8μm的尖端曲率半径的纳米探针接触到第一电极焊盘来进行的。

10. 发明授权

US06781172B2 Semiconductor device with adhesion-improvement capacitor and process for producing the device 失效
标题翻译：具有粘附改善电容器的半导体器件及其制造方法
公开(公告)号：US06781172B2
公开(公告)日：2004-08-24
申请号：US09800493
申请日：2001-03-08
申请人： Hiroshi Moriya , Tomio Iwasaki , Hiroyuki Ohta , Shinpei Iijima , Isamu Asano , Yuzuru Ohji , Yoshitaka Nakamura
发明人： Hiroshi Moriya , Tomio Iwasaki , Hiroyuki Ohta , Shinpei Iijima , Isamu Asano , Yuzuru Ohji , Yoshitaka Nakamura
IPC分类号： H01L2976
CPC分类号： H01L28/60 , H01L27/10814 , H01L28/55
摘要： A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.
摘要翻译：一种配备有信息存储电容器的半导体器件，包括第一电容器电极，氧化物膜，第二电容器电极和以硅为主要构成元素的绝缘膜，其中，第一和第二电容器电极中的至少一个包含作为主要构成元素选自铑，钌，铱，锇和铂中的至少一种元素，并且作为添加元素，选自钯，镍，钴和钛中的至少一种元素，电容器电极和绝缘膜之间的粘附性优异。

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