专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08664722B2 Thin film transistor with metal silicide layer 有权
标题翻译：具有金属硅化物层的薄膜晶体管
公开(公告)号：US08664722B2
公开(公告)日：2014-03-04
申请号：US13288999
申请日：2011-11-04
申请人： Takashi Shingu , Daisuke Ohgarane , Yurika Sato
发明人： Takashi Shingu , Daisuke Ohgarane , Yurika Sato
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L29/66621 , H01L29/458 , H01L29/66757
摘要： In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.
摘要翻译：在制造半导体器件的方法中，形成在绝缘体上的半导体膜掺杂有杂质元素，其深度小于半导体膜的厚度，从而形成杂质掺杂层; 在杂质掺杂层上形成金属硅化物层; 蚀刻金属硅化物层和半导体膜以形成凹部; 并且不掺杂杂质元素并且位于半导体膜的凹部的底部的层被薄化以形成沟道形成区域。此外，在稀薄的非杂质掺杂层上的凹部中形成有栅电极，其间插入有绝缘膜。

2. 发明授权

US08053289B2 Manufacturing method for thin film transistor on insulator 有权
标题翻译：绝缘子薄膜晶体管的制造方法
公开(公告)号：US08053289B2
公开(公告)日：2011-11-08
申请号：US12251596
申请日：2008-10-15
申请人： Takashi Shingu , Daisuke Ohgarane , Yurika Sato
发明人： Takashi Shingu , Daisuke Ohgarane , Yurika Sato
IPC分类号： H01L21/786
CPC分类号： H01L29/66621 , H01L29/458 , H01L29/66757
摘要： In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.
摘要翻译：在制造半导体器件的方法中，形成在绝缘体上的半导体膜掺杂有杂质元素，其深度小于半导体膜的厚度，从而形成杂质掺杂层; 在杂质掺杂层上形成金属硅化物层; 蚀刻金属硅化物层和半导体膜以形成凹部; 并且不掺杂杂质元素并且位于半导体膜的凹部的底部的层被薄化以形成沟道形成区域。此外，在稀薄的非杂质掺杂层上的凹部中形成有栅电极，其间插入有绝缘膜。

3. 发明授权

US08048749B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08048749B2
公开(公告)日：2011-11-01
申请号：US12178356
申请日：2008-07-23
申请人： Tomokazu Yokoi , Atsuo Isobe , Motomu Kurata , Takeshi Shichi , Daisuke Ohgarane , Takashi Shingu
发明人： Tomokazu Yokoi , Atsuo Isobe , Motomu Kurata , Takeshi Shichi , Daisuke Ohgarane , Takashi Shingu
IPC分类号： H01L21/336
CPC分类号： H01L29/66765
摘要： A method for manufacturing a semiconductor device, by which a bottom gate thin film transistor that has an improved S value and a channel forming region with a smaller thickness than that of a source region and a drain region can be manufactured in a simple process. An island-like conductive film is formed over a surface of an insulating substrate in a portion corresponding to a channel forming region, and is covered with an insulating film to form a projection portion. After an amorphous semiconductor film is deposited to cover the projection portion, the amorphous semiconductor film is irradiated with laser light so as to be melted and crystallized. Part of the melted semiconductor over the projection portion flows into regions adjacent to both sides of the projection portion, which results in reduction in thickness of the semiconductor film over the projection portion (channel forming region).
摘要翻译：一种制造半导体器件的方法，通过该方法可以以简单的方法制造具有改善的S值的底栅极薄膜晶体管和具有比源极区和漏极区更小的厚度的沟道形成区。在对应于沟道形成区域的部分的绝缘基板的表面上形成岛状导电膜，并且被绝缘膜覆盖以形成突出部。在沉积非晶半导体膜以覆盖突出部分之后，用激光照射非晶半导体膜以使其熔化并结晶。突出部分上的熔融半导体的一部分流入与突出部分的两侧相邻的区域，这导致半导体膜在突出部分（沟道形成区域）上的厚度减小。

4. 发明授权

US08415228B2 Manufacturing method of SOI substrate and semiconductor device 有权
标题翻译： SOI衬底和半导体器件的制造方法
公开(公告)号：US08415228B2
公开(公告)日：2013-04-09
申请号：US12555825
申请日：2009-09-09
申请人： Kazuya Hanaoka , Takashi Shingu , Taichi Endo
发明人： Kazuya Hanaoka , Takashi Shingu , Taichi Endo
IPC分类号： H01L21/30
CPC分类号： H01L21/76254
摘要： To provide a manufacturing method of a semiconductor device in which, even when the semiconductor device is formed over an SOI substrate which uses a glass substrate, an insulating film and a semiconductor film over the glass substrate are not peeled by stress applied by a conductive film in formation of the conductive film for forming a gate electrode. A semiconductor device is manufactured by the steps of forming a first insulating film over a bond substrate, forming an embrittlement layer by adding ions from a surface of the bond substrate, bonding the bond substrate to a glass substrate with the first insulating film interposed therebetween, separating the bond substrate along the embrittlement layer to form a semiconductor film over the glass substrate with the first insulating film interposed therebetween, removing a peripheral region of the first insulating film and the semiconductor film to expose part of the glass substrate, forming a gate insulating film over and in contact with the semiconductor film and the glass substrate, and forming a stacked conductive film over and in contact with the gate insulating film, in which the stacked conductive film includes a conductive film having a tensile stress and a conductive film having a compressive stress.
摘要翻译：为了提供一种半导体器件的制造方法，其中即使半导体器件形成在使用玻璃衬底的SOI衬底上，绝缘膜和玻璃衬底上的半导体膜也不会被导电膜施加的应力剥离形成用于形成栅电极的导电膜。通过以下步骤制造半导体器件：通过在接合衬底上形成第一绝缘膜，通过从接合衬底的表面添加离子形成脆化层，将接合衬底与第一绝缘膜接合在玻璃衬底上，沿着所述脆化层分离所述接合衬底，以在所述玻璃衬底上形成半导体膜，并且在所述玻璃衬底之间插入所述第一绝缘膜，除去所述第一绝缘膜和所述半导体膜的周边区域，以暴露所述玻璃衬底的一部分，形成栅极绝缘并且与半导体膜和玻璃基板接触并且形成与栅极绝缘膜接触的层叠导电膜，其中层叠导电膜包括具有拉伸应力的导电膜和具有拉伸应力的导电膜压应力。

5. 发明申请

US20080230835A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080230835A1
公开(公告)日：2008-09-25
申请号：US12051645
申请日：2008-03-19
申请人： Takashi Shingu , Hideki Matsukura
发明人： Takashi Shingu , Hideki Matsukura
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78621 , H01L29/41733 , H01L29/458 , H01L29/66757
摘要： It is an object to provide an element structure of a semiconductor device for having a sufficient contact area between an electrode in contact with a source region or a drain region and the source region or the drain region, and a method for manufacturing the semiconductor device with the element structure. An upper electrode is formed over a high-concentration impurity region (the source region or the drain region). A contact hole passing through an interlayer insulating film is formed overlapping with a region where the upper electrode and the high-concentration impurity region are stacked.
摘要翻译：本发明的目的是提供一种半导体器件的元件结构，用于在与源极区域或漏极区域以及源极区域或漏极区域接触的电极之间具有足够的接触面积，以及用于制造具有元素结构。在高浓度杂质区（源区或漏区）上形成上电极。通过层间绝缘膜的接触孔形成为与上部电极和高浓度杂质区域堆叠的区域重叠。

6. 发明授权

US08253252B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08253252B2
公开(公告)日：2012-08-28
申请号：US12051645
申请日：2008-03-19
申请人： Takashi Shingu , Hideki Matsukura
发明人： Takashi Shingu , Hideki Matsukura
IPC分类号： H01L23/48
CPC分类号： H01L29/78621 , H01L29/41733 , H01L29/458 , H01L29/66757
摘要： It is an object to provide an element structure of a semiconductor device for having a sufficient contact area between an electrode in contact with a source region or a drain region and the source region or the drain region, and a method for manufacturing the semiconductor device with the element structure. An upper electrode is formed over a high-concentration impurity region (the source region or the drain region). A contact hole passing through an interlayer insulating film is formed overlapping with a region where the upper electrode and the high-concentration impurity region are stacked.
摘要翻译：本发明的目的是提供一种半导体器件的元件结构，用于在与源极区域或漏极区域以及源极区域或漏极区域接触的电极之间具有足够的接触面积，以及用于制造具有元素结构。在高浓度杂质区（源区或漏区）上形成上电极。通过层间绝缘膜的接触孔形成为与上部电极和高浓度杂质区域堆叠的区域重叠。

7. 发明授权

US08815657B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08815657B2
公开(公告)日：2014-08-26
申请号：US12550540
申请日：2009-08-31
申请人： Suguru Ozawa , Atsuo Isobe , Takashi Hamada , Junpei Momo , Hiroaki Honda , Takashi Shingu , Tetsuya Kakehata
发明人： Suguru Ozawa , Atsuo Isobe , Takashi Hamada , Junpei Momo , Hiroaki Honda , Takashi Shingu , Tetsuya Kakehata
IPC分类号： H01L21/00
CPC分类号： H01L21/76254
摘要： After a single crystal semiconductor layer provided over a base substrate by attaching is irradiated with a laser beam, characteristics thereof are improved by first heat treatment, and after adding an impurity element imparting conductivity to the single crystal semiconductor layer, second heat treatment is performed at lower temperature than that of the first heat treatment.
摘要翻译：在通过附着设置在基底基板上的单晶半导体层通过激光照射之后，通过第一热处理来提高其特性，并且在向单晶半导体层添加赋予导电性的杂质元素之后，进行第二热处理比第一次热处理温度低。

8. 发明授权

US08236668B2 Method for manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US08236668B2
公开(公告)日：2012-08-07
申请号：US12244414
申请日：2008-10-02
申请人： Hideto Ohnuma , Takashi Shingu , Tetsuya Kakehata , Kazutaka Kuriki , Shunpei Yamazaki
发明人： Hideto Ohnuma , Takashi Shingu , Tetsuya Kakehata , Kazutaka Kuriki , Shunpei Yamazaki
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L27/1266 , H01L21/2007 , H01L21/76254 , H01L27/1214 , H01L29/66772
摘要： An object of the present invention is to provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even where a substrate having a low upper temperature limit such as a glass substrate is used. The manufacturing method compromises the steps of preparing a semiconductor substrate provided with a bonding layer formed on a surface thereof and a separation layer formed at a predetermined depth from the surface thereof, bonding the bonding layer to the base substrate having a distortion point of 700° C. or lower so that the semiconductor substrate and the base substrate face each other, and separating a part of the semiconductor substrate at the separation layer by heat treatment in order to form a single-crystal semiconductor layer over the base substrate. In the manufacturing method, a substrate which shrinks isotropically at least by the heat treatment is used as the base substrate.
摘要翻译：本发明的目的是提供一种制造具有半导体层的SOI衬底的方法，即使在使用诸如玻璃衬底的上限温度低的衬底的情况下也可以使用。制造方法损害了制备其表面上形成有接合层的半导体衬底和从其表面形成在预定深度的分离层的步骤，将接合层粘合到具有700°的变形点的基底 C.或更低，使得半导体衬底和基底基板彼此面对，并且通过热处理在分离层处分离半导体衬底的一部分，以在基底衬底上形成单晶半导体层。在制造方法中，使用至少通过热处理各向同性收缩的基板作为基底。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式